AM1808AZCED3 datasheet(154/264 Pages) TI

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AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

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Table 6-68. General Timing Requirements for SPI0 Master Modes (1) (continued)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Input

Polarity = 0, Phase = 0,

Hold

from SPI0_CLK falling

Time,

Polarity = 0, Phase = 1,

SPI0_S

from SPI0_CLK rising

OMI

Polarity = 1, Phase = 0,

tih(SPC_SOMI)M

valid

from SPI0_CLK rising

after

receive

edge of

Polarity = 1, Phase = 1,

SPI0_CL from SPI0_CLK falling

Table 6-69. General Timing Requirements for SPI0 Slave Modes(1)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tc(SPC)S

Cycle Time, SPI0_CLK, All Slave Modes

40(2)

256P

50(2)

256P

60(2)

256P

tw(SPCH)S

Pulse Width High, SPI0_CLK, All Slave Modes

tw(SPCL)S

Pulse Width Low, SPI0_CLK, All Slave Modes

Polarity = 0, Phase = 0,

to SPI0_CLK rising

Setup time, transmit

Polarity = 0, Phase = 1,

data written to SPI

to SPI0_CLK rising

tsu(SOMI_SPC)S

before initial clock

Polarity = 1, Phase = 0,

edge from

to SPI0_CLK falling

master.(3) (4)

Polarity = 1, Phase = 1,

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK rising

Delay, subsequent

Polarity = 0, Phase = 1,

bits valid on

from SPI0_CLK falling

td(SPC_SOMI)S

SPI0_SOMI after

Polarity = 1, Phase = 0,

transmit edge of

from SPI0_CLK falling

SPI0_CLK

Polarity = 1, Phase = 1,

from SPI0_CLK rising

Polarity = 0, Phase = 0,

0.5S-6

0.5S-16

0.5S-20

from SPI0_CLK falling

Output hold time,

Polarity = 0, Phase = 1,

0.5S-6

0.5S-16

0.5S-20

SPI0_SOMI valid

from SPI0_CLK rising

toh(SPC_SOMI)S

after

Polarity = 1, Phase = 0,

receive edge of

0.5S-6

0.5S-16

0.5S-20

from SPI0_CLK rising

SPI0_CLK

Polarity = 1, Phase = 1,

0.5S-6

0.5S-16

0.5S-20

from SPI0_CLK falling

Polarity = 0, Phase = 0,

1.5

to SPI0_CLK falling

Input Setup Time,

Polarity = 0, Phase = 1,

1.5

SPI0_SIMO valid

to SPI0_CLK rising

tsu(SIMO_SPC)S

before

Polarity = 1, Phase = 0,

receive edge of

1.5

to SPI0_CLK rising

SPI0_CLK

Polarity = 1, Phase = 1,

1.5

to SPI0_CLK falling

(1)

P = SYSCLK2 period; S = tc(SPC)S (SPI slave bit clock period)

(2)

This timing is limited by the timing shown or 3P, whichever is greater.

(3)

First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on

SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.

(4)

Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus

cycles must be accounted for to allow data to be written to the SPI module by the CPU.

154

Peripheral Information and Electrical Specifications

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