AM1808AZCED3 datasheet(157/264 Pages) TI

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AM1808

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SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-71. Additional SPI0 Master Timings, 4-Pin Chip Select Option (1) (2) (3) (continued)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Polarity = 0, Phase = 0,

0.5M+P-1

0.5M+P-2

0.5M+P-3

from SPI0_CLK falling

Polarity = 0, Phase = 1,

P-1

P-2

P-3

from SPI0_CLK falling

Delay from final SPI0_CLK edge to master deasserting

td(SPC_SCS)M

SPI0_SCS (6) (7)

Polarity = 1, Phase = 0,

0.5M+P-1

0.5M+P-2

0.5M+P-3

from SPI0_CLK rising

Polarity = 1, Phase = 1,

P-1

P-2

P-3

from SPI0_CLK rising

(6)

Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.

(7)

This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

Table 6-72. Additional SPI0 Master Timings, 5-Pin Option (1) (2) (3)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Polarity = 0, Phase = 0,

0.5M+P+5

0.5M+P+6

from SPI0_CLK falling

Polarity = 0, Phase = 1,

Max delay for slave to deassert

P+5

P+6

from SPI0_CLK falling

SPI0_ENA after final SPI0_CLK edge

td(SPC_ENA)M

to ensure master does not begin the

Polarity = 1, Phase = 0,

0.5M+P+5

0.5M+P+6

next transfer.(4)

from SPI0_CLK rising

Polarity = 1, Phase = 1,

P+5

P+6

from SPI0_CLK rising

Polarity = 0, Phase = 0,

0.5M+P-2

0.5M+P-3

from SPI0_CLK falling

Polarity = 0, Phase = 1,

P-2

P-3

from SPI0_CLK falling

Delay from final SPI0_CLK edge to

td(SPC_SCS)M

master deasserting SPI0_SCS (5) (6)

Polarity = 1, Phase = 0,

0.5M+P-2

0.5M+P-3

from SPI0_CLK rising

Polarity = 1, Phase = 1,

P-2

P-3

from SPI0_CLK rising

Max delay for slave SPI to drive SPI0_ENA valid after master

td(SCSL_ENAL)M asserts SPI0_SCS to delay the master from beginning the next

C2TDELAY+P

transfer,

(1)

These parameters are in addition to the general timings for SPI master modes ( Table 6-69 ).

(2)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPI0_ENA deassertion.

(5)

Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.

(6)

This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

Peripheral Information and Electrical Specifications

157

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