AM1808AZCED3 datasheet(159/264 Pages) TI

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AM1808

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SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-74. Additional SPI0 Slave Timings, 4-Pin Chip Select Option (1) (2) (3)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

td(SCSL_SPC)S

Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave.

P + 1.5

Polarity = 0, Phase = 0,

0.5M+P+4

0.5M+P+5

from SPI0_CLK falling

Polarity = 0, Phase = 1,

P+4

P+5

from SPI0_CLK falling

Required delay from final SPI0_CLK edge before SPI0_SCS is

td(SPC_SCSH)S

deasserted.

Polarity = 1, Phase = 0,

0.5M+P+4

0.5M+P+5

from SPI0_CLK rising

Polarity = 1, Phase = 1,

P+4

P+5

from SPI0_CLK rising

P+17.

tena(SCSL_SOMI)S

Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid

P+20

P+27

P+17.

tdis(SCSH_SOMI)S

Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI

P+20

P+27

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-69 ).

(2)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

Table 6-75. Additional SPI0 Slave Timings, 5-Pin Option (1) (2) (3)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

td(SCSL_SPC)S

Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave.

P + 1.5

Polarity = 0, Phase = 0,

0.5M+P

from SPI0_CLK falling

Polarity = 0, Phase = 1,

P+4

P+5

from SPI0_CLK falling

Required delay from final SPI0_CLK edge before SPI0_SCS is

td(SPC_SCSH)S

deasserted.

Polarity = 1, Phase = 0,

0.5M+P

from SPI0_CLK rising

Polarity = 1, Phase = 1,

P+4

P+5

from SPI0_CLK rising

tena(SCSL_SOMI)S

Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid

P+17.5

P+20

P+27

tdis(SCSH_SOMI)S

Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI

P+17.5

P+20

P+27

tena(SCSL_ENA)S

Delay from master deasserting SPI0_SCS to slave driving SPI0_ENA valid

17.5

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-69 ).

(2)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

Peripheral Information and Electrical Specifications

159

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