AM1808AZCED3 datasheet(160/264 Pages) TI

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AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

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Table 6-75. Additional SPI0 Slave Timings, 5-Pin Option (1) (2) (3) (continued)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Polarity = 0, Phase = 0,

2.5P+17

2.5P+20

2.5P+27

from SPI0_CLK falling

Polarity = 0, Phase = 1,

2.5P+17

2.5P+20

2.5P+27

from SPI0_CLK rising

Delay from final clock receive edge on SPI0_CLK to slave 3-stating

tdis(SPC_ENA)S

or driving high SPI0_ENA.(4)

Polarity = 1, Phase = 0,

2.5P+17

2.5P+20

2.5P+27

from SPI0_CLK rising

Polarity = 1, Phase = 1,

2.5P+17

2.5P+20

2.5P+27

from SPI0_CLK falling

(4)

SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should

be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.

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Peripheral Information and Electrical Specifications

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