AM1808AZCED3 datasheet(164/264 Pages) TI

164 / 264 page

AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

www.ti.com

Table 6-78. Additional(1) SPI1 Master Timings, 4-Pin Enable Option(2) (3)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Polarity = 0, Phase = 0,

3P+5

3P+6

to SPI1_CLK rising

Delay from slave

Polarity = 0, Phase = 1,

0.5M+3P+5

0.5M+3P+6

assertion of SPI1_ENA to SPI1_CLK rising

td(EN A_SPC)M

active to first

Polarity = 1, Phase = 0,

SPI1_CLK from

3P+5

3P+6

to SPI1_CLK falling

master.(4)

Polarity = 1, Phase = 1,

0.5M+3P+5

0.5M+3P+6

to SPI1_CLK falling

Polarity = 0, Phase = 0,

0.5M+P+5

0.5M+P+6

from SPI1_CLK falling

Max delay for slave to

Polarity = 0, Phase = 1,

deassert SPI1_ENA

P+5

P+6

from SPI1_CLK falling

after final SPI1_CLK

td(SPC_ENA)M

edge to ensure master

Polarity = 1, Phase = 0,

0.5M+P+5

0.5M+P+6

does not begin the

from SPI1_CLK rising

next transfer.(5)

Polarity = 1, Phase = 1,

P+5

P+6

from SPI1_CLK rising

(1)

These parameters are in addition to the general timings for SPI master modes ( Table 6-76 ).

(2)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPI1_ENA assertion.

(5)

In the case where the master SPI is ready with new data before SPI1_ENA deassertion.

Table 6-79. Additional(1) SPI1 Master Timings, 4-Pin Chip Select Option(2) (3)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Polarity = 0, Phase = 0,

2P-1

2P-5

2P-6

to SPI1_CLK rising

Polarity = 0, Phase = 1,

Delay from

0.5M+2P-1

0.5M+2P-5

0.5M+2P-6

to SPI1_CLK rising

SPI1_SCS active

td(SCS_SPC)M

to first

Polarity = 1, Phase = 0,

2P-1

2P-5

2P-6

SPI1_CLK(4) (5)

to SPI1_CLK falling

Polarity = 1, Phase = 1,

0.5M+2P-1

0.5M+2P-5

0.5M+2P-6

to SPI1_CLK falling

Polarity = 0, Phase = 0,

0.5M+P-1

0.5M+P-5

0.5M+P-6

from SPI1_CLK falling

Delay from final

Polarity = 0, Phase = 1,

P-1

P-5

P-6

SPI1_CLK edge to from SPI1_CLK falling

td(SPC_SCS)M

master

Polarity = 1, Phase = 0,

deasserting

0.5M+P-1

0.5M+P-5

0.5M+P-6

from SPI1_CLK rising

SPI1_SCS (6) (7)

Polarity = 1, Phase = 1,

P-1

P-5

P-6

from SPI1_CLK rising

(1)

These parameters are in addition to the general timings for SPI master modes ( Table 6-76 ).

(2)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPI1_SCS assertion.

(5)

This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(6)

Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain

asserted.

(7)

This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

164

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Product Folder Link(s): AM1808

AM1808AZCED3 Datasheet(PDF) 164 Page - Texas Instruments

AM1808AZCED3 Datasheet(HTML) 164 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL