AM1808AZCED3 datasheet(166/264 Pages) TI

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AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

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Table 6-80. Additional (1) SPI1 Master Timings, 5-Pin Option (2) (3) (continued)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Polarity = 0, Phase = 0,

3P+5

3P+6

to SPI1_CLK rising

Polarity = 0, Phase = 1,

0.5M+3P+5

0.5M+3P+6

to SPI1_CLK rising

Delay from assertion of SPI1_ENA low to first SPI1_CLK

td(ENA_SPC)M

edge.(10)

Polarity = 1, Phase = 0,

3P+5

3P+6

to SPI1_CLK falling

Polarity = 1, Phase = 1,

0.5M+3P+5

0.5M+3P+6

to SPI1_CLK falling

(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.

Table 6-81. Additional(1) SPI1 Slave Timings, 4-Pin Enable Option(2) (3)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Polarity = 0, Phase = 0,

1.5P-3

2.5P+15

1.5P-10

2.5P+17

1.5P-12

2.5P+19

from SPI1_CLK falling

Polarity = 0, Phase = 1,

–0.5M+1.5P-3

–0.5M+2.5P+15

–0.5M+1.5P-10

–0.5M+2.5P+17

–0.5M+1.5P-12

–0.5M+2.5P+19

Delay from final

from SPI1_CLK falling

td(SPC_ENAH)S SPI1_CLK edge to slave

Polarity = 1, Phase = 0,

deasserting SPI1_ENA.

1.5P-3

2.5P+15

1.5P-10

2.5P+17

1.5P-12

2.5P+19

from SPI1_CLK rising

Polarity = 1, Phase = 1,

–0.5M+1.5P-3

–0.5M+2.5P+15

–0.5M+1.5P-10

–0.5M+2.5P+17

–0.5M+1.5P-12

–0.5M+2.5P+19

from SPI1_CLK rising

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-77 ).

(2)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

Table 6-82. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2) (3)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

td(SCSL_SPC)S

Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave.

P+1.5

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-77 ).

(2)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

166

Peripheral Information and Electrical Specifications

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