AM1808AZCED3 datasheet(167/264 Pages) TI

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AM1808

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SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-82. Additional (1) SPI1 Slave Timings, 4-Pin Chip Select Option (2) (3) (continued)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Polarity = 0, Phase = 0,

0.5M+P+4

0.5M+P+5

0.5M+P+6

from SPI1_CLK falling

Polarity = 0, Phase = 1,

P+4

P+5

P+6

from SPI1_CLK falling

Required delay from final SPI1_CLK edge before

td(SPC_SCSH)S

SPI1_SCS is deasserted.

Polarity = 1, Phase = 0,

0.5M+P+4

0.5M+P+5

0.5M+P+6

from SPI1_CLK rising

Polarity = 1, Phase = 1,

P+4

P+5

P+6

from SPI1_CLK rising

tena(SCSL_SOMI)S

Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid

P+15

P+17

P+19

tdis(SCSH_SOMI)S

Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI

P+15

P+17

P+19

Table 6-83. Additional(1) SPI1 Slave Timings, 5-Pin Option(2) (3)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

td(SCSL_SPC)S

Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave.

P+1.5

Polarity = 0, Phase = 0,

0.5M+P+4

0.5M+P+5

0.5M+P+6

from SPI1_CLK falling

Polarity = 0, Phase = 1,

P+4

P+5

P+6

from SPI1_CLK falling

Required delay from final SPI1_CLK edge before

td(SPC_SCSH)S

SPI1_SCS is deasserted.

Polarity = 1, Phase = 0,

0.5M+P+4

0.5M+P+5

0.5M+P+6

from SPI1_CLK rising

Polarity = 1, Phase = 1,

P+4

P+5

P+6

from SPI1_CLK rising

tena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid

P+15

P+17

P+19

tdis(SCSH_SOMI)S

Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI

P+15

P+17

P+19

tena(SCSL_ENA)S

Delay from master deasserting SPI1_SCS to slave driving SPI1_ENA valid

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-77 ).

(2)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

Peripheral Information and Electrical Specifications

167

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