AM1808AZCED3 datasheet(220/264 Pages) TI

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AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

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6.26 Universal Parallel Port (uPP)

The Universal Parallel Port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated

data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital

converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel). It may

also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve

high-speed digital data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which

its individual channels operate in opposite directions.

The uPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU

overhead during high-speed data transmission. All uPP transactions use the internal DMA to provide data

to or retrieve data from the I/O channels. The DMA controller includes two DMA channels, which typically

service separate I/O channels. The uPP peripheral also supports data interleave mode, in which all DMA

resources service a single I/O channel. In this mode, only one I/O channel may be used.

The features of the uPP include:

•

Programmable data width per channel (from 8 to 16 bits inclusive)

•

Programmable data justification

–

Right-justify with zero extend

–

Right-justify with sign extend

–

Left-justify with zero fill

•

Supports multiplexing of interleaved data during SDR transmit

•

Optional frame START signal with programmable polarity

•

Optional data ENABLE signal with programmable polarity

•

Optional synchronization WAIT signal with programmable polarity

•

Single Data Rate (SDR) or Double data Rate (DDR, interleaved) interface

–

Supports multiplexing of interleaved data during SDR transmit

–

Supports demultiplexing and multiplexing of interleaved data during DDR transfers

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Peripheral Information and Electrical Specifications

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