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AM1808AZCED3 Datasheet(PDF) 227 Page - Texas Instruments |
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AM1808AZCED3 Datasheet(HTML) 227 Page - Texas Instruments |
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227 / 264 page  AM1808 www.ti.com SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010 Table 6-118. Video Port Interface (VPIF) Registers (continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E1 70B0 CH1_VSIZE_CFG0 Channel 1 vertical data size configuration (0) 0x01E1 70B4 CH1_VSIZE_CFG1 Channel 1 vertical data size configuration (1) 0x01E1 70B8 CH1_VSIZE_CFG2 Channel 1 vertical data size configuration (2) 0x01E1 70BC CH1_VSIZE Channel 1 vertical image size DISPLAY CHANNEL 2 REGISTERS 0x01E1 70C0 CH2_TY_STRTADR Channel 2 Top Field luma buffer start address 0x01E1 70C4 CH2_BY_STRTADR Channel 2 Bottom Field luma buffer start address 0x01E1 70C8 CH2_TC_STRTADR Channel 2 Top Field chroma buffer start address 0x01E1 70CC CH2_BC_STRTADR Channel 2 Bottom Field chroma buffer start address 0x01E1 70D0 CH2_THA_STRTADR Channel 2 Top Field horizontal ancillary data buffer start address 0x01E1 70D4 CH2_BHA_STRTADR Channel 2 Bottom Field horizontal ancillary data buffer start address 0x01E1 70D8 CH2_TVA_STRTADR Channel 2 Top Field vertical ancillary data buffer start address 0x01E1 70DC CH2_BVA_STRTADR Channel 2 Bottom Field vertical ancillary data buffer start address 0x01E1 70E0 CH2_SUBPIC_CFG Channel 2 sub-picture configuration 0x01E1 70E4 CH2_IMG_ADD_OFST Channel 2 image data address offset 0x01E1 70E8 CH2_HA_ADD_OFST Channel 2 horizontal ancillary data address offset 0x01E1 70EC CH2_HSIZE_CFG Channel 2 horizontal data size configuration 0x01E1 70F0 CH2_VSIZE_CFG0 Channel 2 vertical data size configuration (0) 0x01E1 70F4 CH2_VSIZE_CFG1 Channel 2 vertical data size configuration (1) 0x01E1 70F8 CH2_VSIZE_CFG2 Channel 2 vertical data size configuration (2) 0x01E1 70FC CH2_VSIZE Channel 2 vertical image size 0x01E1 7100 CH2_THA_STRTPOS Channel 2 Top Field horizontal ancillary data insertion start position 0x01E1 7104 CH2_THA_SIZE Channel 2 Top Field horizontal ancillary data size 0x01E1 7108 CH2_BHA_STRTPOS Channel 2 Bottom Field horizontal ancillary data insertion start position 0x01E1 710C CH2_BHA_SIZE Channel 2 Bottom Field horizontal ancillary data size 0x01E1 7110 CH2_TVA_STRTPOS Channel 2 Top Field vertical ancillary data insertion start position 0x01E1 7114 CH2_TVA_SIZE Channel 2 Top Field vertical ancillary data size 0x01E1 7118 CH2_BVA_STRTPOS Channel 2 Bottom Field vertical ancillary data insertion start position 0x01E1 711C CH2_BVA_SIZE Channel 2 Bottom Field vertical ancillary data size 0x01E1 7120 - 0x01E1 713F - Reserved DISPLAY CHANNEL 3 REGISTERS 0x01E1 7140 CH3_TY_STRTADR Channel 3 Field 0 luma buffer start address 0x01E1 7144 CH3_BY_STRTADR Channel 3 Field 1 luma buffer start address 0x01E1 7148 CH3_TC_STRTADR Channel 3 Field 0 chroma buffer start address 0x01E1 714C CH3_BC_STRTADR Channel 3 Field 1 chroma buffer start address 0x01E1 7150 CH3_THA_STRTADR Channel 3 Field 0 horizontal ancillary data buffer start address 0x01E1 7154 CH3_BHA_STRTADR Channel 3 Field 1 horizontal ancillary data buffer start address 0x01E1 7158 CH3_TVA_STRTADR Channel 3 Field 0 vertical ancillary data buffer start address 0x01E1 715C CH3_BVA_STRTADR Channel 3 Field 1 vertical ancillary data buffer start address 0x01E1 7160 CH3_SUBPIC_CFG Channel 3 sub-picture configuration 0x01E1 7164 CH3_IMG_ADD_OFST Channel 3 image data address offset 0x01E1 7168 CH3_HA_ADD_OFST Channel 3 horizontal ancillary data address offset 0x01E1 716C CH3_HSIZE_CFG Channel 3 horizontal data size configuration 0x01E1 7170 CH3_VSIZE_CFG0 Channel 3 vertical data size configuration (0) 0x01E1 7174 CH3_VSIZE_CFG1 Channel 3 vertical data size configuration (1) 0x01E1 7178 CH3_VSIZE_CFG2 Channel 3 vertical data size configuration (2) 0x01E1 717C CH3_VSIZE Channel 3 vertical image size Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 227 Submit Documentation Feedback Product Folder Link(s): AM1808 |
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