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AM1808AZCED3 Datasheet(PDF) 230 Page - Texas Instruments |
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AM1808AZCED3 Datasheet(HTML) 230 Page - Texas Instruments |
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230 / 264 page  VP_CLKIN0/1 VP_DINx/FIELD/ HSYNC/VSYNC 1 2 VP_CLKOUTx (PositiveEdge Clocking) VP_CLKOUTx (NegativeEdge Clocking) VP_DOUTx 1 2 11 12 4 4 3 AM1808 SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010 www.ti.com Table 6-120. Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs (see Figure 6-74) 1.3V, 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tsu(VDINV-VKIH) Setup time, VP_DINx valid before VP_CLKIN0/1 high 4 6 7 ns 2 th(VKIH-VDINV) Hold time, VP_DINx valid after VP_CLKIN0/1 high 0 0 0 ns Figure 6-74. VPIF Channels 0/1 Video Capture Data and Control Input Timing Table 6-121. Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With Respect to VP_CLKOUT2/3(1) (see Figure 6-75) 1.3V, 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tc(VKO) Cycle time, VP_CLKOUT2/3 13.3 20 37 ns 2 tw(VKOH) Pulse duration, VP_CLKOUT2/3 high 0.4C 0.4C 0.4C ns 3 tw(VKOL) Pulse duration, VP_CLKOUT2/3 low 0.4C 0.4C 0.4C ns 4 tt(VKO) Transition time, VP_CLKOUT2/3 5 5 5 ns Delay time, 11 td(VKOH-VPDOUTV) 8.5 12 17 ns VP_CLKOUT2/3 high to VP_DOUTx valid Delay time, 12 td(VCLKOH-VPDOUTIV) 1.5 1.5 1.5 ns VP_CLKOUT2/3 high to VP_DOUTx invalid (1) C = VP_CLKO2/3 period in ns. Figure 6-75. VPIF Channels 2/3 Video Display Data Output Timing With Respect to VP_CLKOUT2/3 230 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 |
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