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AM1808AZCED3 Datasheet(PDF) 247 Page - Texas Instruments |
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AM1808AZCED3 Datasheet(HTML) 247 Page - Texas Instruments |
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247 / 264 page ![]() GP [ ] asinput n m GPn m [ ] asoutput 4 3 2 1 GP [ ] asinput n m 2 1 AM1808 www.ti.com SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010 6.32.2 GPIO Peripheral Input/Output Electrical Data/Timing Table 6-135. Timing Requirements for GPIO Inputs(1) (see Figure 6-84) 1.3V, 1.2V, 1.1V, 1.0V NO. UNIT MIN MAX 1 tw(GPIH) Pulse duration, GPn[m] as input high 2C(1) (2) ns 2 tw(GPIL) Pulse duration, GPn[m] as input low 2C(1) (2) ns (1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device enough time to access the GPIO register through the internal bus. (2) C=SYSCLK4 period in ns. Table 6-136. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 6-84) 1.3V, 1.2V, 1.1V, 1.0V NO. PARAMETER UNIT MIN MAX 3 tw(GPOH) Pulse duration, GPn[m] as output high 2C(1) (2) ns 4 tw(GPOL) Pulse duration, GPn[m] as output low 2C(1) (2) ns (1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity. (2) C=SYSCLK4 period in ns. Figure 6-84. GPIO Port Timing 6.32.3 GPIO Peripheral External Interrupts Electrical Data/Timing Table 6-137. Timing Requirements for External Interrupts(1) (see Figure 6-85) 1.3V, 1.2V, 1.1V, 1.0V NO. PARAMETER UNIT MIN MAX 1 tw(ILOW) Width of the external interrupt pulse low 2C(1) (2) ns 2 tw(IHIGH) Width of the external interrupt pulse high 2C(1) (2) ns (1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have the device recognize the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to access the GPIO register through the internal bus. (2) C=SYSCLK4 period in ns. Figure 6-85. GPIO External Interrupt Timing Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 247 Submit Documentation Feedback Product Folder Link(s): AM1808 |
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