AM1808AZCED3 datasheet(252/264 Pages) TI

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AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

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Table 6-143. ARM Debug Features

Category

Hardware Feature

Availability

Software breakpoint

Unlimited

Up to 14 HWBPs, including:

2 precise(1) HWBP inside ARM core which are shared with watch points.

Basic Debug

Hardware breakpoint

8 imprecise(1) HWBPs from ETM’s address comparators, which are shared with trace

function, and can be used as watch points.

4 imprecise(1) HWBPs from ICECrusher.

Up to 6 watch points, including:

2 from ARM core which is shared with HWBPs and can be associated with a data.

Watch point

8 from ETM’s address comparators, which are shared with trace function, and

HWBPs.

2 from ARM core which is shared with HWBPs.

Analysis

Watch point with Data

8 watch points from ETM can be associated with a data comparator, and ETM has

total 4 data comparators.

Counters/timers

3x32-bit (1 cycle ; 2 event)

External Event Trigger In

External Event Trigger Out

Address range for trace

Data qualification for trace

System events for trace control

Trace Control

Counters/Timers for trace control

2x16-bit

State Machines/Sequencers

1x3-State State Machine

Context/Thread ID Comparator

Independent trigger control units

Capture depth PC

4k bytes ETB

On-chip Trace

Capture depth PC + Timing

4k bytes ETB

Capture

Application accessible

(1)

Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints

will halt the processor some number of cycles after the selected instruction depending on device conditions.

6.34.1 JTAG Port Description

The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,

TDI, and TDO), a return clock (RTCK) due to the clocking requirements of the ARM926EJ-S and

emulation signals EMU0 and EMU1. TRST holds the debug and boundary scan logic in reset when pulled

low (its default state). Since TRST has an internal pull-down resistor, this ensures that at power up the

device functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST

should be driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be

performed while the TRST pin is pulled low.

Table 6-144. JTAG Port Description

TYPE

NAME

DESCRIPTION

When asserted (active low) causes all test and debug logic in the device to be reset

TRST

Test Logic Reset

along with the IEEE 1149.1 interface

This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic.

TCK

Test Clock

Depending on the emulator attached to , this is a free running clock or a gated clock

depending on RTCK monitoring.

Synchronized TCK. Depending on the emulator attached to, the JTAG signals are

RTCK

Returned Test Clock

clocked from RTCK or RTCK is monitored by the emulator to gate TCK.

TMS

Test Mode Select

Directs the next state of the IEEE 1149.1 test access port state machine

TDI

Test Data Input

Scan data input to the device

TDO

Test Data Output

Scan data output of the device

252

Peripheral Information and Electrical Specifications

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