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EP7311 Datasheet(PDF) 5 Page - Cirrus Logic |
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EP7311 Datasheet(HTML) 5 Page - Cirrus Logic |
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5 / 58 page ![]() DS506F1 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 5 EP7311 High-Performance, Low-Power System on Chip List of Figures Figure 1. A Maximum EP7309 Based System ..............................................................................................................11 Figure 2. Legend for Timing Diagrams .........................................................................................................................14 Figure 3. Static Memory Single Read Cycle Timing Measurement ...............................................................................16 Figure 4. Static Memory Single Write Cycle Timing Measurement ...............................................................................17 Figure 5. Static Memory Burst Read Cycle Timing Measurement ................................................................................18 Figure 6. Static Memory Burst Write Cycle Timing Measurement ................................................................................19 Figure 7. SSI1 Interface Timing Measurement .............................................................................................................20 Figure 8. SSI2 Interface Timing Measurement .............................................................................................................21 Figure 9. LCD Controller Timing Measurement ............................................................................................................22 Figure 10. JTAG Timing Measurement .........................................................................................................................23 Figure 11. 208-Pin LQFP Package Outline Drawing ....................................................................................................24 Figure 12. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ..........................................................................25 Figure 13. 204-Ball TFBGA Package ............................................................................................................................29 Figure 14. 256-Ball PBGA Package ..............................................................................................................................38 List of Tables Table 1. Power Management Pin Assignments ..............................................................................................................6 Table 2. Static Memory Interface Pin Assignments ........................................................................................................6 Table 3. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7 Table 4. DAI Interface Pin Assignments .........................................................................................................................7 Table 5. CODEC Interface Pin Assignments ..................................................................................................................7 Table 6. SSI2 Interface Pin Assignments .......................................................................................................................7 Table 7. Serial Interface Pin Assignments ......................................................................................................................8 Table 8. LCD Interface Pin Assignments ........................................................................................................................8 Table 9. Keypad Interface Pin Assignments ...................................................................................................................8 Table 10. Interrupt Controller Pin Assignments ..............................................................................................................8 Table 11. Real-Time Clock Pin Assignments ..................................................................................................................9 Table 12. PLL and Clocking Pin Assignments ................................................................................................................9 Table 13. DC-to-DC Converter Interface Pin Assignments .............................................................................................9 Table 14. General Purpose Input/Output Pin Assignments ............................................................................................9 Table 15. Hardware Debug Interface Pin Assignments ..................................................................................................9 Table 16. LED Flasher Pin Assignments ........................................................................................................................9 Table 17. DAI/SSI2/CODEC Pin Multiplexing ...............................................................................................................10 Table 18. Pin Multiplexing .............................................................................................................................................10 Table 19. 208-Pin LQFP Numeric Pin Listing ...............................................................................................................26 Table 20. 204-Ball TFBGA Ball Listing .........................................................................................................................31 Table 21. 256-Ball PBGA Ball Listing ...........................................................................................................................39 Table 22. JTAG Boundary Scan Signal Ordering .........................................................................................................43 Table 23. Acronyms and Abbreviations ........................................................................................................................48 Table 24. Unit of Measurement .....................................................................................................................................48 Table 25. Pin Description Conventions .........................................................................................................................49 |
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