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EP7311 Datasheet(PDF) 22 Page - Cirrus Logic |
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EP7311 Datasheet(HTML) 22 Page - Cirrus Logic |
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22 / 58 page ![]() 22 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) DS506F1 EP7311 High-Performance, Low-Power System on Chip Static Memory Single Read Cycle Note: 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2. Address, Halfword, Word, and Write hold state until next cycle. EXPCLK nCS A nMWE HALF- WORD WORD D WRITE nMOE t CSd t Ad t CSh t MOEh t Dh t Ds t HWd t WDd t WRd t MOEd EXPRDY t EXh t EXs Figure 7. Static Memory Single Read Cycle Timing Measurement |
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