IP4251_52_53_54_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 6 May 2009

8 of 16

NXP Semiconductors

IP4251/52/53/54

Integrated 4-, 6- and 8-channel passive filter network

Due to the optimized silicon dice and package design, all channels in a single package

show a very good matching performance as the insertion loss for a channel at the

package side (e.g. ch1 to ch16) is nearly identical with the center channels (e.g. ch4 to

ch13). Typical measurements results are shown in Figure 3 to Figure 6 for the different

devices.

7.2 Selection

The IP425x family is mainly designed as EMI/RFI filters for multi-channel interfaces. The

selection of one of the filter devices has to be performed dependent on the maximum

clock frequency, driver strength, capacitive load of the sink, and also the maximum

applicable rise and fall times.

7.2.1 SD(HC) and MMC memory interface

The Secure Digital High Capacity (SDHC) memory card interface standard specification

and the MultiMediaCard (MMC) (JESD 84A43) standard specification recommend a rise

and fall time of 25 % to 62.5 % (62.5 % to 25 % respectively) of 3 ns or less for the input

signal of the receiving interface side.

Assuming a typical capacitance of about 20 pF for the SDHC memory card itself, and

approximately 4 pF to 7 pF for the PCB and the card holder, IP4252CZ12-6 (6 channels,

all relevant interface pins such as CLK, CMD, and DAT0 to DAT3/CD. Please refer to

Figure 7 for a general example of the implementation of the IP4252 in an SD(HC) card

interface.

In case additional channels such as write-protect or a mechanical card detection switch

offers two additional channels.

(1) IP4253CZ16 - ch1 to ch16

(2) IP4253CZ16 - ch4 to ch13

(1) IP4254CZ16 - ch4 to ch13

(2) IP4254CZ16 - ch1 to ch16

Fig 5.

IP4253 frequency response curves

Fig 6.

IP4254 frequency response curves

001aaj610

−30

−20

−40

−10

0

(dB)

−50

f (MHz)

10

(1)

(2)

001aaj611

−30

−20

−40

−10

0

(dB)

−50

f (MHz)

10

(1)

(2)