LPC2930 datasheet(21/98 Pages) NXP

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LPC2930_3

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Product data sheet

Rev. 03 — 16 April 2010

21 of 98

NXP Semiconductors

LPC2930

ARM9 microcontroller with CAN, LIN, and USB

6.7 External Static Memory Controller (SMC)

The LPC2930 contains an external Static Memory Controller (SMC) which provides an

interface for external (off-chip) memory devices.

Key features are:

• Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and

external I/O devices

• Asynchronous page-mode read operation in non-clocked memory subsystems

• Asynchronous burst-mode read access to burst-mode ROM devices

• Independent configuration for up to eight banks, each up to 16 MB

• Programmable bus-turnaround (idle) cycles (one to 16)

• Programmable read and write wait states (up to 32), for static RAM devices

• Programmable initial and subsequent burst-read wait state for burst-ROM devices

• Programmable write protection

• Programmable burst-mode operation

• Programmable external data width: 8 bits, 16 bits or 32 bits

• Programmable read-byte lane enable control

6.7.1 Description

The SMC simultaneously supports up to eight independently configurable memory banks.

Each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting

SRAM, ROM, burst-ROM memory, or external I/O devices.

A separate chip select output is available for each bank. The chip select lines are

configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory

addressing. Table 9 shows how the 32-bit system address is mapped to the external bus

memory base addresses, chip selects, and bank internal addresses.

Table 8.

CGU1 base clock and branch clock overview

Base clock

Branch clock name

Parts of the device clocked by this

branch clock

BASE_OUT_CLK

CLK_OUT_CLK

CLK_OUT pin

BASE_USB_CLK

CLK_USB_CLK

USB clock

BASE_USB_I2C_CLK

CLK_USB_I2C_CLK

USB OTG I2C clock

Table 9.

External memory-bank address bit description

32-bit

system

address bit

field

Symbol

Description

31 to 29

BA[2:0]

external static-memory base address (three most significant bits);

the base address can be found in the memory map; see Ref. 1. This

field contains ‘010’ when addressing an external memory bank.

28 to 26

CS[2:0]

chip select address space for eight memory banks; see Ref. 1.

25 and 24

always ‘00’; other values are ‘mirrors’ of the 16 MB bank address.

23 to 0

A[23:0]

16 MB memory banks address space

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