LPC2930 datasheet(13/98 Pages) NXP

13 / 98 page

LPC2930_3

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Product data sheet

Rev. 03 — 16 April 2010

13 of 98

NXP Semiconductors

LPC2930

ARM9 microcontroller with CAN, LIN, and USB

[1]

Bidirectional pad; analog port; plain input; 3-state output; slew rate control; 5 V tolerant; TTL with hysteresis; programmable pull-up /

pull-down / repeater.

[2]

USB pad.

[3]

For LPC2930 only, these are the boot control pins for configuring the external memory bus width. Use a weak pull-up/pull-down resistor

(

≈1 kΩ to 10 kΩ) to set level. See Table 11.

[4]

Analog pad; Analog input/output.

[5]

Analog I/O pad.

Functional description

6.1 Architectural overview

The LPC2930 consists of:

• An ARM968E-S processor with real-time emulation support.

• An AMBA multilayer Advanced High-performance Bus (AHB) for interfacing to the

on-chip memory controllers.

• Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller

and the Power, Clock and Reset Control cluster (also called subsystem).

• Three ARM Peripheral Buses (APB - a compatible super set of ARM's AMBA

advanced peripheral bus) for connection to on-chip peripherals clustered in

subsystems.

• One ARM Peripheral Bus for event router and system control.

The LPC2930 configures the ARM968E-S processor in little-endian byte order. All

peripherals run at their own clock frequency to optimize the total system power

consumption. The AHB-to-APB bridge used in the subsystems contains a write-ahead

buffer one transaction deep. This implies that when the ARM968E-S issues a buffered

write action to a register located on the APB side of the bridge, it continues even though

the actual write may not yet have taken place. Completion of a second write to the same

subsystem will not be executed until the first write is finished.

P0[21]/IN2[5]/

PMAT2[3]/A17

201[5]

GPIO 0, pin 21

ADC2 IN5

PWM2 MAT3

EXTBUS A17

P0[22]/IN2[6]/

PMAT2[4]/A18

202[5]

GPIO 0, pin 22

ADC2 IN6

PWM2 MAT4

EXTBUS A18

VSS(IO)

203

P0[23]/IN2[7]/

PMAT2[5]/A19

204[5]

GPIO 0, pin 23

ADC2 IN7

PWM2 MAT5

EXTBUS A19

P2[20]/

PCAP2[0]/D18

205[1]

GPIO 2, pin 20

SPI2 SDO

PWM2 CAP0

EXTBUS D18

VDD(CORE)

206

1.8 V power supply for digital core

VSS(CORE)

207

ground for digital core

TDI

208[1]

IEEE 1149.1 data in, pulled up internally

Table 3.

LQFP208 pin assignment …continued

Pin name

Description

Function 0

(default)

Function 1

Function 2

Function 3

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