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[1]

All ports are in input only (high impedance) state after power-up.

[2]

The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is

xx11 0000.

[3]

After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[4]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[5]

The only reset source that affects these SFRs is power-on reset.

RTCL

Real-time clock register low

D3H

00[5]

0000 0000

SP

Stack pointer

81H

07

0000 0111

SPCTL

SPI control register

E2H

SSIG

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

04

0000 0100

SPSTAT

SPI status register

E1H

SPIF

WCOL

------

00

00xx xxxx

SPDAT

SPI data register

E3H

00

0000 0000

TAMOD

Timer 0 and 1 auxiliary mode

8FH

-------

T0M2

00

xxx0 xxx0

Bit address

8F

8E

8D

8C

8B

8A

89

88

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

----

00

0000 0000

TH0

Timer 0 high

8CH

00

0000 0000

TH1

Timer 1 high

8DH

00

0000 0000

TL0

Timer 0 low

8AH

00

0000 0000

TL1

Timer 1 low

8BH

00

0000 0000

TMOD

Timer 0 and 1 mode

89H

-

-

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00

0000 0000

TRIM

Internal oscillator trim register

96H

-

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[4] [5]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

-

-

WDRUN

WDTOF

WDCLK

[3] [5]

WDL

Watchdog load

C1H

FF

1111 1111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

Table 7.

* indicates SFRs that are bit addressable.

Name

Description

SFR

addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary