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P89LPC913 Datasheet(PDF) 53 Page - NXP Semiconductors |
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P89LPC913 Datasheet(HTML) 53 Page - NXP Semiconductors |
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53 / 66 page  P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 28 September 2007 53 of 66 NXP Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 11. Dynamic characteristics Table 14. Dynamic characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = −40 °C to +85 °C for industrial, −40 °C to +125 °C for extended, unless otherwise specified.[1] Symbol Parameter Conditions Variable clock fosc =12MHz Unit Min Max Min Max fosc(RC) internal RC oscillator frequency nominal f = 7.3728 MHz; trimmed to ±1% at Tamb =25 °C 7.189 7.557 7.189 7.557 MHz fosc(WD) internal watchdog oscillator frequency nominal f = 400 kHz 320 520 320 520 kHz Crystal oscillator (P89LPC912, P89LPC913) fosc oscillator frequency 0 12 - - MHz Tcy(clk) clock cycle time see Figure 25 83 - - - ns fCLKLP low-power select clock frequency 0 8 - - MHz Glitch filter tgr glitch rejection P1.5/RST pin - 50 - 50 ns any pin except P1.5/RST - 15 - 15 ns tsa signal acceptance P1.5/RST pin 125 - 125 - ns any pin except P1.5/RST 50 - 50 - ns External clock (P89LPC912, P89LPC913) tCHCX clock HIGH time see Figure 25 33 Tcy(clk) − tCLCX 33 - ns tCLCX clock LOW time see Figure 25 33 Tcy(clk) − tCHCX 33 - ns tCLCH clock rise time see Figure 25 -8 - 8 ns tCHCL clock fall time see Figure 25 -8 - 8 ns Shift register (UART mode 0 - P89LPC913, P89LPC914) TXLXL serial port clock cycle time see Figure 24 16Tcy(clk) - 1333 - ns tQVXH output data set-up to clock rising edge see Figure 24 13Tcy(clk) - 1083 - ns tXHQX output data hold after clock rising edge see Figure 24 -Tcy(clk) + 20 - 103 ns tXHDX input data hold after clock rising edge see Figure 24 -0 - 0 ns tXHDV input data valid to clock rising edge see Figure 24 150 - 150 - ns SPI interface fSPI SPI operating frequency 2.0 MHz (slave) 0 CCLK ⁄ 6 0 2.0 MHz 3.0 MHz (master) - CCLK ⁄ 4 - 3.0 MHz TSPICYC SPI cycle time see Figure 26, 27, 28, 29 slave 6 ⁄ CCLK - 500 - ns master 4 ⁄ CCLK - 333 - ns |
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