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PCA9575 Datasheet(PDF) 9 Page - NXP Semiconductors |
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PCA9575 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 38 page ![]() PCA9575_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 9 November 2009 9 of 38 NXP Semiconductors PCA9575 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.3 Command register Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9575, which will be stored in the Command register. The lowest 4 bits are used as a pointer to determine which register will be accessed. Only a Command register code with the 4 least significant bits equal to the 16 allowable values as defined in Table 3 “Register summary” will be acknowledged. Reserved or undefined command codes will not be acknowledged. At power-up, this register defaults to 00h, with the AI bit set to logic 0, and the lowest 4 bits set to logic 0. If the Auto-Increment flag is set (AI = 1), the 4 least significant bits of the Command register are automatically incremented after a read or write. This allows the user to program and/or read the 16 command registers (listed in Table 3) sequentially. It will then roll over to register 00h after the last register is accessed and the selected registers will be overwritten or re-read. If the Auto-Increment flag is cleared (AI = 0), the 4 least significant bits are not incremented after data is read or written, only one register will be repeatedly read or written. 7.4 Register definitions Reset state = 00h Remark: The Command register does not apply to Software Reset I2C-bus address. Fig 8. Command register 002aad568 AI 0 0 0 D3 D2 D1 D0 register address Auto-Increment flag Table 3. Register summary Register number D3 D2 D1 D0 Name Type Function 00h 0 0 0 0 IN0 read only Input port 0 register 01h 0 0 0 1 IN1 read only Input port 1 register 02h 0 0 1 0 INVRT0 read/write Polarity inversion port 0 register 03h 0 0 1 1 INVRT1 read/write Polarity inversion port 1 register 04h 0 1 0 0 BKEN0 read/write Bus-hold enable 0 register 05h 0 1 0 1 BKEN1 read/write Bus-hold enable 1 register 06h 0 1 1 0 PUPD0 read/write Pull-up/pull-down selector port 0 register 07h 0 1 1 1 PUPD1 read/write Pull-up/pull-down selector port 1 register 08h 1 0 0 0 CFG0 read/write Configuration port 0 register 09h 1 0 0 1 CFG1 read/write Configuration port 1 register 0Ah 1 0 1 0 OUT0 read/write Output port 0 register 0Bh 1 0 1 1 OUT1 read/write Output port 1 register 0Ch 1 1 0 0 MSK0 read/write Interrupt mask port 0 register |
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