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PCF8531 Datasheet(PDF) 17 Page - NXP Semiconductors |
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PCF8531 Datasheet(HTML) 17 Page - NXP Semiconductors |
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17 / 44 page  PCF8531_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 13 June 2008 17 of 44 NXP Semiconductors PCF8531 34 x 128 pixel matrix driver 8.1 Addressing Data is written in bytes into the RAM matrix of the PCF8531 as shown in Figure 8, Figure 9 and Figure 10. The display RAM has a matrix of 34 × 128 bits. The columns are addressed by the address pointer. The address ranges are X 0 to X 127 (7Fh) and Y 0 to Y 5 (5h). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1), the Y address increments after each byte (see Figure 9). After the last Y address (Y = 4), Y wraps around to 0 and X increments to address the next column. In horizontal addressing mode (V = 0), the X address increments after each byte (see Figure 10). After the last X address (X = 127), X wraps around to 0 and Y increments to address the next Fig 7. DDRAM to display data mapping top of LCD mgs468 bank 0 bank 1 bank 2 bank 3 bank 4 R32 R24 R16 R8 R0 R33 (icon row) bank 5 LCD DDRAM |
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