PCF8531 datasheet(32/44 Pages) NXP

32 / 44 page

PCF8531_4

Product data sheet

Rev. 04 — 13 June 2008

32 of 44

NXP Semiconductors

PCF8531

34 x 128 pixel matrix driver

14. Dynamic characteristics

[1]

ffr =fclk(ext)/480 or fosc/480.

[2]

A reset is generated if tw(RESL) > 3 ns (see Figure 20).

[3]

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH, with an

input voltage swing of VSS to VDD.

[4]

Cb = total capacitance of one bus line in pF.

Table 16.

Dynamic characteristics

VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 =VSS2 =0V; VDD1 to VDD3 ≤ VLCD ≤ 9.0 V; Tamb = −40 °C

to +85

°C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ffr(LCD)

LCD frame frequency

VDD = 3.0 V

[1] 40

135

fosc

oscillator frequency

kHz

fclk(ext)

external clock frequency

kHz

tw(RESL)

RES LOW pulse width

[2] 300

tsu(RESL)

RES LOW set-up time

µs

Serial bus interface (see Figure 21)[3]

fSCL

SCL clock frequency

400

kHz

tLOW

LOW period of the SCL clock

1.3

µs

tHIGH

HIGH period of the SCL clock

0.6

µs

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

0.9

rise time of both SDA and SCL signals

[4] 20 + 0.1Cb -

0.3

µs

fall time of both SDA and SCL signals

[4] 20 + 0.1Cb -

0.3

µs

capacitive load for each bus line

400

tSU;STA

set-up time for a repeated START condition

0.6

µs

tHD;STA

hold time (repeated) START condition

0.6

µs

tSU;STO

set-up time for STOP condition

0.6

µs

tSP

pulse width of spikes that must be

suppressed by the input ﬁlter

on bus

tBUF

bus free time between a STOP and START

condition

1.3

µs

Fig 20. Reset timing

mgs476

tw(RESL)

tsu(RESL)

VIL

VDD

RES

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