PCF8531 datasheet(28/44 Pages) NXP

28 / 44 page

PCF8531_4

Product data sheet

Rev. 04 — 13 June 2008

28 of 44

NXP Semiconductors

PCF8531

34 x 128 pixel matrix driver

11.2 I2C-bus protocol

This driver does not support ‘read’. The PCF8531 is a slave receiver. Therefore, it only

responds when R/W = 0 in the slave address byte.

Before any data is transmitted on the I2C-bus, the device that must respond is addressed

ﬁrst. Two 7-bit slave addresses (011 1100 and 011 1101) are reserved for the PCF8531.

The least signiﬁcant bit of the slave address is set by connecting the input SA0 to either

logic 0 (VSS) or logic 1 (VDD).

The I2C-bus protocol is shown in Figure 18.

The sequence is initiated with a START condition (S) from the I2C-bus master, and is

followed by the slave address. All slaves with the corresponding address acknowledge in

parallel, all others ignore the I2C-bus transfer. After acknowledgement, one or more

command words follow, which deﬁne the status of the addressed slaves. A command

word consists of a control byte, which deﬁnes Co and RS, plus a data byte (see Figure 19

and Table 11).

The last control byte is tagged with a cleared most signiﬁcant bit, the continuation bit Co.

The control and data bytes are also acknowledged by all addressed slaves on the bus.

After the last control byte, depending on the RS bit setting, either a series of display data

bytes or command data bytes may follow. If the RS bit was set to logic 1, these display

bytes are stored in the display RAM at the address speciﬁed by the data pointer.

The data pointer is automatically updated and the data is directed to the intended

PCF8531 device. If the RS bit of the last control byte was set to logic 0, these command

bytes will be decoded and the setting of the device will be changed according to the

received commands. The acknowledgement after each byte is made only by the

addressed PCF8531. At the end of the transmission, the I2C-bus master issues a STOP

condition (P).

Fig 18. Slave address and control byte

mgs474

011110

SA0

slave address

R/W

XXXXXX

control byte

Fig 19. Master transmits to slave receiver; write mode

mgs475

S 011110

acknowledge

from PCF8531

acknowledge

from PCF8531

acknowledge

from PCF8531

acknowledge

from PCF8531

acknowledge

from PCF8531

control byte

data byte

≥ 0 bytes

1 byte

slave address

MSB . . . . . . . . . . . LSB

≥ 0 bytes

A P

R/W

control byte

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