PCF8531 datasheet(20/44 Pages) NXP

20 / 44 page

PCF8531_4

Product data sheet

Rev. 04 — 13 June 2008

20 of 44

NXP Semiconductors

PCF8531

34 x 128 pixel matrix driver

• Register settings remain unchanged

9.2.2 V

When V = 0 the horizontal addressing is selected. The data is written into the DDRAM as

shown in Figure 10. When V = 1 the vertical addressing is selected. The data is written

into the DDRAM as shown in Figure 9. Icon data is written independently of V when

Y address is 5.

9.3 Set Y address

Bits Y2, Y1 and Y0 deﬁne the Y address vector of the display RAM (see Table 6).

9.4 Set X address

The X address points to the columns. The range of X is 0 to 127 (7Fh).

9.5 Set multiplex rate

M[1:0] selects the multiplex rate (see Table 7).

9.6 Display control (D, E and IM)

Bits D and E select the display mode (see Table 13). Bit IM (see Table 12) sets the display

to icon mode.

9.7 Set bias system

Different multiplex rates require different bias settings. Bias settings are programmed by

BS[2:0], which sets the binary number n. The optimum value for n is given by:

Supported values of n are given in Table 8. Table 9 shows the intermediate bias voltages.

Table 6.

Y address

Bank

0000

0011

0102

0113

1004

1015 (icons)

Table 7.

Multiplex rates

Multiplex rate

1:17

1:26

1:34

muxrate

–

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