12F629 datasheet(68/136 Pages) MICROCHIP

68 / 136 page

PIC12F629/675

DS41190G-page 68

 2010 Microchip Technology Inc.

9.7

Power-Down Mode (Sleep)

The Power-down mode is entered by executing a

SLEEP

instruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running

•PD bit in the STATUS register is cleared

•TO bit is set

• Oscillator driver is turned off

• I/O ports maintain the status they had before

Sleep was executed (driving high, low, or

high-impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD, or VSS, with no external

circuitry drawing current from the I/O pin and the com-

parators and CVREF should be disabled. I/O pins that

are high-impedance inputs should be pulled high or low

externally to avoid switching currents caused by float-

ing inputs. The T0CKI input should also be at VDD or

VSS for lowest current consumption. The contribution

from on-chip pull-ups on GPIO should be considered.

The MCLR pin must be at a logic high level (VIHMC).

9.7.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

External Reset input on MCLR pin

Watchdog Timer Wake-up (if WDT was enabled)

Interrupt from GP2/INT pin, GPIO change, or a

peripheral interrupt.

The first event will cause a device Reset. The two latter

events are considered a continuation of program exe-

cution. The TO and PD bits in the STATUS register can

be used to determine the cause of device Reset. The

PD bit, which is set on power-up, is cleared when Sleep

is invoked. TO bit is cleared if WDT Wake-up occurred.

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake-up through an interrupt event, the correspond-

ing interrupt enable bit must be set (enabled). Wake-up

is regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction, then branches to the interrupt

address (0004h). In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have an NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

FIGURE 9-13:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Note:

It should be noted that a Reset generated

by a WDT Time-out does not drive MCLR

pin low.

Note:

If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the correspond-

ing interrupt flag bits set, the device will

immediately wake-up from Sleep. The

SLEEP

instruction is completely executed.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2

0004h

0005h

Dummy cycle

TOST(2)

PC + 2

Note

XT, HS or LP Oscillator mode assumed.

TOST = 1024TOSC (drawing not to scale). Approximately 1

s delay will be there for RC Osc mode. See Section 12 for wake-up from

Sleep delay in INTOSC mode.

GIE =

1 assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.

CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference.

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