12F629 datasheet(105/136 Pages) MICROCHIP

105 / 136 page

 2010 Microchip Technology Inc.

DS41190G-page 105

PIC12F629/675

FIGURE 12-11:

PIC12F675 A/D CONVERSION TIMING (SLEEP MODE)

TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE)

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

130

TAD

A/D Clock Period

1.6

—

sVREF 3.0V

3.0*

—

sVREF full range

130

TAD

A/D Internal RC

Oscillator Period

3.0*

6.0

9.0*

s

ADCS<1:0> = 11 (RC mode)

At VDD = 2.5V

2.0*

4.0

6.0*

sAt VDD = 5.0V

131

TCNV

Conversion Time

(not including

Acquisition Time)(1)

—11

—

TAD

132

TACQ

Acquisition Time

(Note 2)

11.5

—

s

The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

changed by more than 1 LSb (i.e.,

4.1 mV @ 4.096V) from the last

sampled voltage (as stored on

CHOLD).

134

TGO

Q4 to A/D Clock

Start

—TOSC/2 + TCY

—

If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEP instruction to be

executed.

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25

C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 7.1 “A/D Configuration and Operation” for minimum conditions.

131

130

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

134

132

1 TCY

(TOSC/2 + TCY)(1)

1 TCY

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