56F8023 datasheet(32/157 Pages) FREESCALE

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56F8033/56F8023 Data Sheet, Rev. 6

Freescale Semiconductor

The 56F8000 family devices’ on-chip clock synthesis module has the following registers:

•

Control Register (OCCS_CTRL)

•

Divide-by Register (OCCS_DIVBY)

•

Status Register (OCCS_STAT)

•

Shutdown Register (OCCS_SHUTDN)

•

Oscillator Control Register (OCCS_OCTRL)

For more information on these registers, please refer to the 56F802X and 56F803X Peripheral Reference

Manual.

3.4 Internal Clock Source

An internal relaxation oscillator can supply the reference frequency when an external frequency source or

crystal is not used. It is optimized for accuracy and programmability while providing several power-saving

configurations which accommodate different operating conditions. The internal relaxation oscillator has

very little temperature and voltage variability. To optimize power, the architecture supports a standby state

and a power-down state.

During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the

PLLCR word is set to 0). Application code can then also switch to the external clock source and power

down the internal oscillator, if desired. If a changeover between internal and external clock sources is

required at power-on, the user must ensure that the clock source is not switched until the desired external

clock source is enabled and stable.

To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator

can be incrementally adjusted to within + 0.078% of 8MHz by trimming an internal capacitor. Bits 0-9 of

the OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset

value to increase or decrease capacitance. Each unit added or subtracted changes the output frequency by

about 0.078% of 8MHz, allowing incremental adjustment until the desired frequency accuracy is achieved.

The center frequency of the internal oscillator is calibrated at the factory to 8MHz and the TRIM value is

stored in the Flash information block and loaded to the FMOPT1 register at reset. When using the

relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM.

For further information, see the 56F802X and 56F803X Peripheral Reference Manual.

3.5 Crystal Oscillator

The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in a

frequency range of 4-8MHz, specified for the external crystal. Figure 3-1 shows a typical crystal oscillator

circuit. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters

determine the component values required to provide maximum stability and reliable start-up. The load

capacitance values used in the oscillator circuit design should include all stray layout capacitances. The

crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins

to minimize output distortion and start-up stabilization time.

56F8023 Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc

56F8023 Datasheet(HTML) 32 Page - Freescale Semiconductor, Inc

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