56F8023 datasheet(89/157 Pages) FREESCALE

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56F8033/56F8023 Data Sheet, Rev. 6

Freescale Semiconductor

6.3.11.2

Comparator A Clock Stop Disable (CMPA_SD)—Bit 14

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

6.3.11.3

Digital-to-Analog Converter 0 Clock Stop Disable (DAC1_SD)—Bit 13

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

6.3.11.4

Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

6.3.11.5

Reserved—Bit 11

This bit field is reserved. It must be set to 0.

6.3.11.6

Analog-to-Digital Converter Clock Stop Disable (ADC_SD)—Bit 10

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

6.3.11.7

Reserved—Bits 9–7

This bit field is reserved. Each bit must be set to 0.

6.3.11.8

Inter-Integrated Circuit Clock Stop Disable (I2C_SD)—Bit 6

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

6.3.11.9

Reserved—Bit 5

This bit field is reserved. It must be set to 0.

6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)—Bit 4

•

0 = The clock is disabled during Stop mode

•

1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0

6.3.11.11 Reserved—Bit 3

This bit field is reserved. It must be set to 0.

56F8023 Datasheet(PDF) 89 Page - Freescale Semiconductor, Inc

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