56F8035 datasheet(74/161 Pages) FREESCALE

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56F8035/56F8025 Data Sheet, Rev. 6

Freescale Semiconductor

5.6.10

Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Figure 5-12 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

5.6.10.1

Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0

to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.6.11

Fast Interrupt 0 Vector Address High Register (FIVAH0)

Figure 5-13 Fast Interrupt 0 Vector Address High Register (FIVAH0)

5.6.11.1

Reserved—Bits 15–5

This bit field is reserved. Each bit must be set to 0.

5.6.11.2

Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0

The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0

to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.6.12

Fast Interrupt 1 Match Register (FIM1)

Figure 5-14 Fast Interrupt 1 Match Register (FIM1)

5.6.12.1

Reserved—Bits 15–6

This bit field is reserved. Each bit must be set to 0.

5.6.12.2

Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service

routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table

first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast

Base + $9

Read

FAST INTERRUPT 0 VECTOR ADDRESS LOW

Write

RESET

00000

0000000

0000

Base + $A

Read

FAST INTERRUPT 0 VECTOR

ADDRESS HIGH

Write

RESET

00000

0000000

0000

Base + $B

Read

FAST INTERRUPT 1

Write

RESET

00000

0000000

0000

56F8035 Datasheet(PDF) 74 Page - Freescale Semiconductor, Inc

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