56F8035 datasheet(84/161 Pages) FREESCALE

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56F8035/56F8025 Data Sheet, Rev. 6

Freescale Semiconductor

6.3.2

SIM Reset Status Register (SIM_RSTAT)

This read-only register is updated upon any system reset and indicates the cause of the most recent reset.

It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External

Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On

Reset and subsequently is synchronously updated based on the precedence level of reset inputs. Only the

most recent reset source will be indicated if multiple resets occur. If multiple reset sources assert

simultaneously, the highest-precedence source will be indicated. The precedence from highest to lowest is

Power-On Reset, External Reset, COP Loss of Reference Reset, COP Time-Out Reset, and Software

Reset. Power-On Reset is always set during a Power-On Reset; however, Power-On Reset will be cleared

and External Reset will be set if the external reset pin is asserted or remains asserted after the Power-On

Reset has deasserted.

Figure 6-3 SIM Reset Status Register (SIM_RSTAT)

6.3.2.1

Reserved—Bits 15–7

This bit field is reserved. Each bit must be set to 0.

6.3.2.2

Software Reset (SWR)—Bit 6

When set, this bit indicates that the previous system reset occurred as a result of a software reset (written

1 to SWRST bit in the SIM_CTRL register).

6.3.2.3

COP Time-Out Reset (COP_TOR)—Bit 5

When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly

(COP) module signaling a COP time-out reset. If COP_TOR is set as code starts executing, the COP reset

vector in the vector table will be used. Otherwise, the normal reset vector is used.

6.3.2.4

COP Loss of Reference Reset (COP_LOR)—Bit 4

When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly

(COP) module signaling a loss of COP reference clock reset. If COP_LOR is set as code starts executing,

the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.

6.3.2.5

External Reset (EXTR)—Bit 3

When set, this bit indicates that the previous system reset was caused by an external reset.

6.3.2.6

Power-On Reset (POR)—Bit 2

This bit is set during a Power-On Reset.

Base + $1

Read

SWR

COP_

TOR

COP_

LOR

EXTR

POR

Write

RESET

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