56F8035 datasheet(79/161 Pages) FREESCALE

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Introduction

56F8035/56F8025 Data Sheet, Rev. 6

Freescale Semiconductor

5.7.2

Description of Reset Operation

5.7.2.1

Reset Handshake Timing

The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is

asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET

is released. The general timing is shown in Figure 5-22.

Figure 5-22 Reset Interface

5.7.3

ITCN After Reset

After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,

except the core IRQs with fixed priorities:

•

Illegal Instruction

•

SW Interrupt 3

•

HW Stack Overflow

•

Misaligned Long Word Access

•

SW Interrupt 2

•

SW Interrupt 1

•

SW Interrupt 0

•

SW Interrupt LP

These interrupts are enabled at their fixed priority levels.

Part 6 System Integration Module (SIM)

6.1 Introduction

The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls

distribution of resets and clocks and provides a number of control features. The System Integration

Module’s functions are discussed in more detail in the following sections.

RES

CLK

VAB

PAB

RESET_VECTOR_ADR

READ_ADR

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