56F8035 datasheet(89/161 Pages) FREESCALE

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56F8035/56F8025 Data Sheet, Rev. 6

Freescale Semiconductor

6.3.9.3

Digital-to-Analog Clock Enable 1 (DAC1)—Bit 13

•

0 = The clock is not provided to the DAC1 module (the DAC1 module is disabled)

•

1 = The clock is enabled to the DAC1 module

6.3.9.4

Digital-to-Analog Clock Enable 0 (DAC0)—Bit 12

•

0 = The clock is not provided to the DAC0 module (the DAC0 module is disabled)

•

1 = The clock is enabled to the DAC0 module

6.3.9.5

Reserved—Bit 11

This bit field is reserved. It must be set to 0.

6.3.9.6

Analog-to-Digital Converter Clock Enable (ADC)—Bit 10

•

0 = The clock is not provided to the ADC module (the ADC module is disabled)

•

1 = The clock is enabled to the ADC module

6.3.9.7

Reserved—Bits 9–7

This bit field is reserved. Each bit must be set to 0.

6.3.9.8

Inter-Integrated Circuit IPBus Clock Enable (I2C)—Bit 6

•

0 = The clock is not provided to the I2C module (the I2C module is disabled)

•

1 = The clock is enabled to the I2C module

6.3.9.9

Reserved—Bit 5

This bit field is reserved. It must be set to 0.

6.3.9.10

QSCI 0 Clock Enable (QSCI0)—Bit 4

•

0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled)

•

1 = The clock is enabled to the QSCI0 module

6.3.9.11

Reserved—Bit 3

This bit field is reserved. It must be set to 0.

6.3.9.12

QSPI 0 Clock Enable (QSPI0)—Bit 2

•

0 = The clock is not provided to the QSPI0 module (the QSPI0 module is disabled)

•

1 = The clock is enabled to the QSPI0 module

6.3.9.13

Reserved—Bit 1

This bit field is reserved. It must be set to 0.

6.3.9.14

PWM Clock Enable (PWM)—Bit 0

•

0 = The clock is not provided to the PWM module (the PWM module is disabled)

56F8035 Datasheet(PDF) 89 Page - Freescale Semiconductor, Inc

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