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LM26480 Datasheet(PDF) 18 Page - National Semiconductor (TI) |
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LM26480 Datasheet(HTML) 18 Page - National Semiconductor (TI) |
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18 / 30 page ![]() Faults Occurring in Counter Delay After Startup 30040407 The above timing diagram details the Power Good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2 are internal signals derived from the output of two com- parators. Each comparator has been trimmed as follows: Comparator Level Buck Supply Level HIGH Greater than 91% LOW Less than 82% The circuits for EN1 and RDY1 are symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 will also work for EN2 and RDY2 and vice versa. If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay counter (50 μs, 50 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. NPOR is then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this interval the nPOR signal ignores this event. If either RDY1or RDY2 were to go LOW at t3 then the pro- grammable delay is triggered again. www.national.com 18 |
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