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LM26480 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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LM26480 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 30 page  Pin Descriptions LLP Pin No. Name I/O Type Description 1 VINLDO12 I PWR Analog Power for Internal Functions (VREF, BIAS, I2C, Logic) 2 SYNC I G/(D) Frequency Synchronization pin which allows the user to connect an external clock signal to synchronize the PMIC internal oscillator. Default OFF and must be grounded when not used. Part number LM26480SQ-BF has this feature enabled. 3 NPOR O D nPOR Power on reset pin for both Buck1 and Buck 2. Open drain logic output 100K pullup resistor. nPOR is pulled to ground when the voltages on these supplies are not good. See nPOR section for more info. 4 GND_SW1 G G Buck1 NMOS Power Ground 5 SW1 O PWR Buck1 switcher output pin 6 VIN1 I PWR Power in from either DC source or Battery to Buck1 7 ENSW1 I D Enable Pin for Buck1 switcher, a logic HIGH enables Buck1. Pin cannot be left floating. 8 FB1 I A Buck1 input feedback terminal 9 GND_C G G Non-switching core ground pin 10 AVDD I PWR Analog Power for Buck converters 11 FB2 I A Buck2 input feedback terminal 12 ENSW2 I D Enable Pin for Buck2 switcher, a logic HIGH enables Buck2. Pin cannot be left floating. 13 VIN2 I PWR Power in from either DC source or Battery to Buck2 14 SW2 O PWR Buck2 switcher output pin 15 GND_SW2 G G Buck2 NMOS 16 ENLDO2 I D LDO2 enable pin, a logic HIGH enables LDO2. Pin cannot be left floating. 17 ENLDO1 I D LDO1 enable pin, a logic HIGH enables LDO1. Pin cannot be left floating. 18 GND_L G G LDO ground 19 VINLDO1 I PWR Power in from either DC source or battery to LDO1 20 LDO1 O PWR LDO1 Output 21 FBL1 I A LDO1 Feedback Terminal 22 FBL2 I A LDO2 Feedback Terminal 23 LDO2 O PWR LDO Output 24 VINLDO2 I PWR Power in from either DC source or battery to LDO2. DAP DAP GND GND Connection isn't necessary for electrical performance, but it is recommended for better thermal dissipation. A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin Power Block Operation Note Power Block Input Enabled Disabled VINLDO12 VIN+ VIN+ Always Powered AVDD VIN+ VIN+ Always Powered VIN1 VIN+ VIN+ or 0V VIN2 VIN+ VIN+ or 0V VINLDO1 ≤ VIN+ ≤ VIN+ If Enabled, Min VIN is 1.74V VINLDO2 ≤ VIN+ ≤ VIN+ If Enabled, Min VIN is 1.74V VIN+ is the largest potential voltage on the device. www.national.com 4 |
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