11-60
RF2905
Rev B11 010516
11
Pin
Function
Description
Interface Schematic
39
OSC E
This pin is connected directly to the emitter of the reference oscillator
transistors.
See pin 38.
40
OSC B1
This pin is connected directly to the reference oscillator 1 transistor
base. The intended reference oscillator configuration is a modified Col-
pitts.
See pin 38.
41
LOOP FLT
Output of the charge pump, and input to the VCO control. An RC net-
work from this pin to ground is used to establish the PLL bandwidth.
42
VREF P
Bypass pin for the prescaler reference voltage. A 33nF capacitor to
ground is needed to suppress reference spurs in the device. This value
may be different for different PCB arrangements.
43
LOCK DET
This pin provides an analog output indicating the lock status of the PLL.
The amplitude of this signal is typically 200mVPP around a DC level of
VCC-0.1V.
44
VCC1
This pin is used to supply DC bias to the LNA, Mixer, first IF Amp, and
Bandgap reference. A RF bypass capacitor should be connected
directly to this pin and returned to ground. A 22pF capacitor is recom-
mended for 915MHz applications. A 68pF capacitor is recommended
for 433MHz applications.
45
PRESCL
OUT
Dual-modulus/Dual-divide prescaler output. The output can be inter-
faced to an external PLL IC for additional flexibility in frequency pro-
gramming.
46
VCC3
This pin is used to supply DC bias and collector current to the transmit-
ter PA. A RF bypass capacitor should be connected directly to this pin
and returned to ground. A 22pF capacitor is recommended for 915MHz
applications. A 68pF capacitor is recommended for 433MHz applica-
tions.
47
LVL ADJ
This pin is used to vary the transmitter output power. An output level
adjustment range greater than 12dB is provided through analog volt-
age control of this pin. DC current of the transmitter power amp ia also
reduced with output power. This pin MUST be low when the transmitter
is disabled.
48
PLL ENABL This pin is used to power up or down the VCO and PLL. A logic high
(PLLENABL> 2.0V) powers up the VCO and PLL electronics. A logic
low (PLLENABL<1.0V) powers down the PLL and VCO.
LOOP FLT
V
CC
LOCK DET
20 k
Ω
V
CC
PRESCL
OUT
400
4k
Ω
LVL ADJ
40 k
Ω
50 k
Ω
PLL ENABL
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
