SA9109B

12/18

sames

Programming procedure:

The PGM pin is pulled low and the PCLK pin should be clocked with an external

clock. The programming data on the PDTA pin must be stable during the rising edge

of the clock signal on PCLK.

The clock signal on PCLK should not exceed 200 kHz and does not have to be

synchronised with the oscillator frequency (FOSC).

Programming mode is interrupted if PGM goes high.

Memory Reset

In programming mode (while PGM is pulled low) if PCLK is left floating and

PDTA = 0, the internal clock of the SA9109B will ensure that default values are set.

For default conditions all of the RAM locations are set to 0 and the value of the slope

is set to 11389.

The minimum time period for a complete reset cycle is determined by:

t

322 *

64

FOSC

Where FOSC = Oscillator frequency (2MHz......4MHz)

If the recommended crystal frequency of 3.5795MHz is used, this will result in a

minimum reset time of 5.8ms.

The specified signal levels on pins PGM, PCLK and PDTA must remain stable for

the entire reset cycle period.

PDTA

BIT-N0

W ORD-NO

DR-01257

29

1

31

30

11

1

28

27

1

PCLK

PGM

10

24

1

1

1

26

25

0

23

1