AD5755 datasheet(11/34 Pages) AD

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Preliminary Technical Data

AD5755/AD5735

Rev. PrG | Page 11 of 34

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to

100 mA do not cause SCR latch-up.

Table 5.

Parameter

Rating

AVDD to AGND, DGND

−0.3 V to +33 V

AVSS to AGND, DGND

+0.3 V to −28 V

AVDD to AVSS

−0.3 V to +60 V

AVcc to AGND

−0.3 V to +7 V

DVDD to DGND

−0.3 V to +7 V

Digital Inputs to DGND

−0.3 V to DVDD + 0.3 V or

+7 V (whichever is less)

Digital Outputs to DGND

−0.3 V to DVDD + 0.3 V

REFIN/REFOUT to AGND

−0.3 V to AVDD + 0.3 V or +7

V (whichever is less)

VOUT A,B,C,D to AGND

AVSS to VBOOST or 33V if using

the DC-DC circuitry.

−VSENSEA,B,C,D / +VSENSEA,B,C,D to AGND

AVSS to VBOOST or 33V if using

the DC-DC circuitry.

COMPLVA,B,C,D to AGND

0.3 V to +5 V

IOUT A,B,C,D to AGND

AVSS to VBOOST or 33V if using

the DC-DC circuitry.

RSETA,B,C,D to AGND

−0.3 V to AVDD + 0.3 V or +7

V (whichever is less)

SWA,B,C,D / VBOOSTA,B,C,D to AGND

−0.3 to +33 V

COMPDCDC_A,B,C,D to AGND

−0.3 V to +5 V

AGND, GNDSWA,B,C,D to DGND

−0.3 V to +0.3 V

Operating Temperature Range (TA)

Industrial1

−40°C to +105°C

Storage Temperature Range

−65°C to +150°C

Junction Temperature (TJ max)

125°C

64-Lead LFCSP

θJA Thermal Impedance2

20°C/W

Power Dissipation

(TJmax – TA)/θJA

Lead Temperature

JEDEC Industry Standard

Soldering

J-STD-020

1 Power dissipated on chip must be derated to keep the junction temperature

below 125°C

2 Based on a JEDEC 4 layer test board

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

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