AD5755 datasheet(17/34 Pages) AD

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Preliminary Technical Data

AD5755/AD5735

Rev. PrG | Page 17 of 34

SERIAL INTERFACE

The AD5755/AD5735 is controlled over a versatile 3-wire serial

interface that operates at clock rates of up to 30 MHz and is

compatible with SPI®, QSPI™, MICROWIRE™, and DSP

standards. Data coding is always straight binary.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

device MSB first as a 24-bit word under the control of a serial

clock input, SCLK. Data is clocked in on the falling edge of

SCLK.

There are two ways in which the DAC outputs can be updated

as outlined below.

Individual DAC Updating

In this mode, LDAC is held low while data is being clocked into

the DAC Data Register. The addressed DAC output is updated

on the rising edge of SYNC.

Simultaneous Updating of All DACs

In this mode, LDAC is held high while data is being clocked

into the DAC Data Register. Only the first write to each

channels data register will be valid after LDAC is brought high.

Any subsequent writes while LDAC is still held high will be

ignored. All the DAC outputs are updated by taking LDAC low

any time after SYNC has been taken high.

Figure 16. Simplified Serial Interface of Input Loading Circuitry for One DAC

Channel

TRANSFER FUNCTION

Table 10 shows the input code to ideal output voltage

relationship for the AD5755 for straight binary data coding -

±10v output range shown.

Table 7. Ideal Output Voltage to Input Code Relationship

Digital Input

Analog Output

Straight Binary Data Coding

MSB

LSB VOUT

1111

+2 VREF × (32767/32768)

1111

1110

+2 VREF × (32766/32768)

1000

0000

0 V

0000

0001

−2 VREF × (32766/32768)

0000

−2 VREF × (32767/32768)

VOUT

DAC

INTERFACE

LOGIC

OUTPUT

I/V AMPLIFIER

LDAC

SDO

SDIN

16-BIT

DAC

VREFIN

SYNC

INPUT

SCLK

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