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Preliminary Technical Data

AD5755/AD5735

Rev. PrG | Page 31 of 34

Within a channel the Vout & Iout stages share a common Vboost

supply so that the outputs of the Iout & Vout stages can be tied

together.

DC-DC On-Board Switch

The AD5755/AD5735 contains a 0.5ohm internal switch . The

switch current is monitored on a pulse by pulse basis & is

limited to 0.8A peak current.

DC-DC Switching Frequency and Phase

The AD5755/AD5735 DCDC switching frequency can be

selected from the DCDC Control Register to be 250Khz,

400Khz, 649kHz or 812kHz. The phasing of the channels can

also be adjusted so that the DCDCs can clock on different edges

(See Table 32). For typical applications a 250Khz frequency is

recommended. At light loads (low output current & small load

resistor) the DCDC enters a pulse skipping mode to minimize

switching power dissipation.

DC-DC Inductor Selection

For typical 4-20mA applications a 10uH inductor combined

with a switching frequency of 250Khz will allow up to 24mA to

be driven into a load resistance of up to 1kΩ with an AVcc

supply from 2.7 to 5.5v. The inductor must be able to handle the

peak current without saturating at the maximum ambient

temperature.

If an alternative Inductor/Switching frequency is preferred then

one must ensure that the DCDC continues to operates in DCM

mode and that the inductor current is less than 0.8A.

OUT

PEAK

OUT

−

max

min

max

min

max

min

max

)

(

)

(

Where:

IPEAKmax=Maximum Peak Current (0.8A limit)

FSW=Switching Frequency set in the DCDC Control Register.

η = efficiency (Assume = 0.8)

DC-DC External schottky selection

The AD5755/AD5735 requires an external schottky for correct

operation. Ensure the schottky is rated to handle the maximum

reverse breakdown expected in operation & that the rectifier

maximum junction temperature is not exceeded. The diode

average current = Iload current.

DC-DC Compensation Capacitors

As the DCDC operates in DCM the uncompensated transfer

function is essentially a single pole transfer function. The pole

frequency is determined by Cout, Vin, Vout & Iload. The

AD5755/AD5735 uses an external capacitor in conjunction

with an internal 150k resistor to compensate the regulator loop.

For typical 4-20mA applications connect a 10nF capacitor from

each of the COMPDCDC_A/_B/_C/_D pins to GND.

DC-DC Input and Output Capacitor Selection

The output capacitor effects ripple voltage of the DCDC

converter & also indirectly limits the maximum slew rate at

which the channel output current can rise. The ripple voltage is

caused by a combination of the capacitance & ESR (equivalent

series resistance) of the capacitor. For the AD5755/AD5735 a

ceramic capacitor of 4.7µF is recommended for typical

applications. Larger capacitors or paralled capacitors will

improve the ripple at the expense of reduced slew rate.

The input capacitor will provide much of the dynamic current

required for the DCDC converter & should also be a low ESR

component. For the AD5755/AD5735 a ceramic capacitor of

10µF is recommended for typical applications. Ceramic

capacitors must be chosen carefully as they can exhibit a large

sensitivity to DC bias voltages & temperature. X5R or X7R

dielectrics are preferred as these capacitors remain stable over

wider operating voltage & temperature ranges.

Iout Slew Rate when using the DC-DC

When the AD5755/AD5735 is configured in Iout mode & a step

increase in output current is programmed then the DCDC

converter must increase its output voltage so that Vboost ≈

Iout*Rload+2v. This requires that the output capacitor of the

DCDC circuit must also be charge to the new voltage. The

amount of power required to do this is 0.5*C*(Vnew-Vold).

Figure 7. And Figure 8.show Iout settling for a 0 to 24mA step

into a 1kohm load for different caps & inductor/switching

frequency.

AD5755 Datasheet(PDF) 31 Page - Analog Devices

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