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AD5755BCPZx Datasheet(PDF) 32 Page - Analog Devices

Part # AD5755BCPZx
Description  Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control
PDF  34 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5755BCPZx Datasheet(HTML) 32 Page - Analog Devices

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AD5755/AD5735
Preliminary Technical Data
Rev. PrG | Page 32 of 34
APPLICATIONS INFORMATION
PRECISION VOLTAGE REFERENCE SELECTION
To achieve the optimum performance from the
AD5755/AD5735 over its full operating temperature range, a
precision voltage reference must be used. Thought should be
given to the selection of a precision voltage reference. The
voltage applied to the reference inputs is used to provide a
buffered reference for the DAC cores. Therefore, any error in
the voltage reference is reflected in the outputs of the device.
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, temperature coefficient of the output voltage,
long term drift, and output voltage noise.
Initial accuracy error on the output voltage of an external
reference could lead to a full-scale error in the DAC. Therefore,
to minimize these errors, a reference with low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR425, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim
adjustment could be used at temperature to trim out any error.
Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
The temperature coefficient of a reference’s output voltage
affects INL, DNL, and TUE. A reference with a tight
temperature coefficient specification should be chosen to
reduce the dependence of the DAC output voltage on ambient
conditions.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered.
Choosing a reference with as low an output noise voltage as
practical for the system resolution required is important.
Precision voltage references such as the ADR435 (XFET design)
produce low output noise in the 0.1 Hz to 10 Hz region.
However, as the circuit bandwidth increases, filtering the output
of the reference may be required to minimize the output noise.
Table 40. Some Recommended Precision References
Part
No.
Initial
Accuracy
(mV
Max)
Long-Term
Drift (ppm
Typ)
Temp
Drift
(ppm/°C
Max)
0.1 Hz to 10
Hz Noise
(µV p-p
Typ)
ADR435
±6
30
3
3.4
ADR425
±6
50
3
3.4
ADR02
±5
50
3
15
ADR395
±6
50
25
5
AD586
±2.5
15
10
4
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads connect a
0.01µF capacitor between IOUT and GND. This will ensure
stability with loads beyond 50mH. There is no maximum
capacitance limit. The capacitive component of the load may
cause slower settling, though this may be masked by the settling
time of the AD5755/AD5735.
TRANSIENT VOLTAGE PROTECTION
The AD5755/AD5735 contains ESD protection diodes which
prevent damage from normal handling. The industrial control
environment can, however, subject I/O circuits to much higher
transients. In order to protect the AD5755/AD5735 from
excessively high voltage transients , external power diodes and a
surge current limiting resistor may be required, as shown in
Figure 21. The constraint on the resistor value is that during
normal operation the output level at IOUT must remain within
its voltage compliance limit of AVDD – 2.5V and the two
protection diodes and resistor must have appropriate power
ratings.
Figure 21. Output Transient Voltage Protection
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5755/AD5735 is via a serial
bus that uses a protocol compatible with microcontrollers and
DSP processors. The communications channel is a 3-wire
minimum interface consisting of a clock signal, a data signal,
and a latch signal. The AD5755/AD5735 require a 24-bit data-
word with data valid on the falling edge of SCLK.
The DAC output update is initiated on either the rising edge of
LDAC or, if LDAC is held low, on the rising edge of SYNC. The
contents of the registers can be read using the readback
function.
AD5755/AD5735 TO ADSP-BF527 INTERFACE
The AD5755/AD5735 can be connected directly to the SPORT
interface of the ADSP-BF527, an Analog Devices, Inc., Blackfin®
DSP. Figure 22 shows how the SPORT interface can be
connected to control the AD5755/AD5735.
IOUT
GND
AVDD
RP
RLOAD
AVDD
AD5755



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