AD5755BCPZX datasheet(29/34 Pages) AD

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Preliminary Technical Data

AD5755/AD5735

Rev. PrG | Page 29 of 34

ASYNCHRONOUS CLEAR

CLEAR is an active high edge sensitive input that allows the

output to be cleared to a pre programmed 16 bit code. This code

is user programmable via a per-channel 16 bit Clear Code

In order for a channel to clear, that channel must be enabled to

be cleared via the CLR_EN bit in the channels DAC Control

output will remain in its current state independent of the

CLEAR pin level.

When the CLEAR signal is returned low, the relevant outputs

remains cleared until a new value is programmed.

PACKET ERROR CHECKING

To verify that data has been received correctly in noisy

environments, the AD5755/AD5735 offers the option of packet

error checking based on an 8-bit (CRC-8) cyclic redundancy

check. The device controlling the AD5755/AD5735 should

generate an 8-frame check sequence using the polynomial

)

(

This is added to the end of the data word, and 32 bits are sent to

the AD5755/AD5735 before taking SYNC high. If the

AD5755/AD5735 sees a 32-bit frame, it will perform the error

check when SYNC goes high. If the check is valid, then the data

will be written to the selected register. If the error check fails,

the FAULT pin will go low and the PEC ERROR bit in the Status

will return high (assuming there are no other faults) and the

PEC ERROR bit will be cleared automatically.

The PEC can be used for both transmit and receive of data

packets. If Status Readback During Write is enabled, the ‘PEC’

values returned during the Status Readback During Write

should be ignored. All other PEC values will be valid though

and the user can still use the normal readback operation to

monitor Status Register activity with PEC.

WATCHDOG TIMER

If enabled, an on chip watchdog timer will generate an alert

signal if 0x195 has not been written to the Software Register

within the programmed timeout period. This feature is useful to

ensure communication has not been lost between the MCU and

the AD5755/AD5735 and that these datapath lines are working

properly (i.e. SDI/SCLK/SYNC). If 0x195 is not received by the

Software Register within the timeout period, the ALERT pin

will signal a fault condition. The ALERT signal is active high

and can be connected directly to the CLEAR pin to enable a

CLEAR in the event that data communications are lost from the

MCU.

The watchdog timer is enabled and the timeout period

(50,100,150 or 200ms) set in the control register (See Table 25).

OUTPUT ALERT

The AD5755/AD5735 is equipped with a ALERT pin, this is An

active high CMOS output. The AD5755/AD5735 has an

internal watchdog timer. If enabled, it will monitor SPI

communications. If 0x195 is not received by the Software

active.

INTERNAL REFERENCE

The AD5755/AD5735 contains an integrated +5V voltage

reference with initial accuracy of ±2mV max and a temperature

drift coefficient of ±5 ppm max. The reference voltage is

buffered and externally available for use elsewhere within the

system.

EXTERNAL CURRENT SETTING RESISTOR

Referring to Figure 15, R1 is an internal sense resistor as part of

the voltage to current conversion circuitry. The stability of the

output current value over temperature is dependent on the

stability of the value of R1. As a method of improving the

stability of the output current over temperature an external

15kΩ low drift resistor can be connected to the RSET pin of the

AD5755/AD5735 to be used instead of the internal resistor R1.

The external resistor is selected via the DAC Control register.

See Table 27.

SLEW RATE CONTROL

The Slew Rate Control feature of the AD5755/AD5735 allows

the user to control the rate at which the output value changes.

This feature is available on both the current and voltage

outputs. With the slew rate control feature disabled the output

value will change at a rate limited by the output drive circuitry

and the attached load. If the user wishes to reduce the slew rate

this can be achieved by enabling the slew rate control feature.

With the feature enabled via the SREN bit of the Slew Rate

Control Register, (See Table 33) the output, instead of slewing

directly between two values, will step digitally at a rate defined

by two parameters accessible via the Slew Rate Control Register

as shown in Table 33. The parameters are SR_CLOCK and

SR_STEP. SR_CLOCK defines the rate at which the digital slew

will be updated, e.g. if the selected update rate is 8KHz the

output will update every 125µs, in conjunction with this the

SR_STEP defines by how much the output value will change at

each update. Together both parameters define the rate of change

of the output value. Table 38 and Table 39 outline the range of

values for both the SR_CLOCK and SR_STEP parameters.

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