Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

AD5755BCPZx Datasheet(PDF) 8 Page - Analog Devices

Part # AD5755BCPZx
Description  Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control
PDF  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5755BCPZx Datasheet(HTML) 8 Page - Analog Devices

Back Button AD5755BCPZx Datasheet HTML 4Page - Analog Devices AD5755BCPZx Datasheet HTML 5Page - Analog Devices AD5755BCPZx Datasheet HTML 6Page - Analog Devices AD5755BCPZx Datasheet HTML 7Page - Analog Devices AD5755BCPZx Datasheet HTML 8Page - Analog Devices AD5755BCPZx Datasheet HTML 9Page - Analog Devices AD5755BCPZx Datasheet HTML 10Page - Analog Devices AD5755BCPZx Datasheet HTML 11Page - Analog Devices AD5755BCPZx Datasheet HTML 12Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 34 page
background image
AD5755/AD5735
Preliminary Technical Data
Rev. PrG | Page 8 of 34
TIMING CHARACTERISTICS
AVDD = 15V, AVSS = -15V, VBOOSTA,B,C,D = +10.8 V to +33 V, DVDD = AVCC = 2.7 V to 5.5 V, DCDC disabled, AGND = DGND =
GNDSWA,B,C,D = 0 V, REFIN= +5, VOUT : RL = 1kΩ, CL = 220pF, IOUT : RL = 300Ω, all specifications TMIN to TMAX unless otherwise noted.
Table 4.
Parameter1, 2,3
Limit at TMIN, TMAX
Unit
Description
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK high time
t3
13
ns min
SCLK low time
t4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t5
13
ns min
24/32nd SCLK falling edge to SYNC rising edge
t6
198
ns min
SYNC high time
t7
5
ns min
Data setup time
t8
5
ns min
Data hold time
t9
20
µs min
SYNC rising edge to LDAC falling edge (all DACs updated or any
channel has digital slew rate control enabled)
5
µs min
SYNC rising edge to LDAC falling edge (single DAC updated)
t10
10
ns min
LDAC pulse width low
t11
500
ns max
LDAC falling edge to DAC output response time
t12
See AC Performance
Characteristics
µs max
DAC output settling time
t13
10
ns min
CLEAR high time
t14
TBD
µs max
CLEAR activation time
t15
25
ns max
SCLK rising edge to SDO valid (CL SDO = 35 pF)
t16
20
µs min
SYNC rising edge to DAC output response time (LDAC = 0) (all DACs
updated)
5
µs min
SYNC rising edge to DAC output response time (LDAC = 0) (single
DAC updated)
t17
500
ns min
LDAC falling edge to SYNC rising edge
t18
700
ns min
RESET pulse width
t19
20
µs min
SYNC high to next SYNC low (Ramp enabled)
5
µs min
SYNC high to next SYNC low (Ramp disabled)
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3 See Figure 2 , Figure 3 , Figure 4 and Figure 5



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com