Preliminary Technical Data

AD5755/AD5735

Rev. PrG | Page 23 of 34

CONTROL REGISTERS

When writing to a data register the following format must be used:

Table 23. Writing to a control register

MSB

LSB

D23 D22

D21

D20 D19 D18 D17

D16

D15

D14

D13

D12to D0

R/W DUT_AD1 DUT_AD0 1

1

1

DAC_AD1 DAC_AD0 CREG2 CREG1 CREG0

See Table 10 for configuration on bits D23 to D16. The control registers are addressed by setting the DREG bits to DREG2 = 1, DREG1 =

1, DREG0=1 and then setting the CREG2, CREG1 and CREG0 bits to the appropriate decode address for that register as per Table 24

below. These CREG bits select between the various control registers.

Table 24. Register Access Decode

CREG2, (D15)

CREG1, (D14)

CREG0, (D13)

0

0

0

Slew Rate Control Register (one per channel)

0

0

1

Main Control Register

0

1

0

DAC Control Register (one per channel)

0

1

1

DC-DC Control Register

1

0

0

Software Register (one per channel)

MAIN CONTROL REGISTER

CREG2, CREG1, CREG0 are set to ‘0,0,1’ to select the Main Control Register. The Main Control Register options are shown below.

Table 25. Programming the Main Control Register

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3 to D0

0

0

1

POC

STATREAD

EWD

WD1

WD0

X

ShtCctLim

OUTEN ALL

DC-DC ALL

X

Table 26. Main Control Register Functions.

Option

Description

POC

The POC bit decides the state of the VOUT channel during normal operation. It’s default value is 0.

POC Bit = 0. The output will go to the value set by the POC pin when the current out channel is enabled.

STATREAD

Enable status readback during a write. See Features section.

STATREAD =1, Enable

STATREAD =0, Disable

EWD

Enable Watchdog Timer. See features section for more information.

EWD=1, Enable Watchdog

EWD=0, Disable Watchdog

WD1, WD0

Timeout Select Bits. Used to select timeout period for watchdog timer.

WD1

WD0

0

0

5ms

0

1

10ms

1

0

100ms

1

1

200ms

ShtCctLim

0=15ma

1=8ma

OUTEN ALL

Enables the output on all 4 DAC simultaneously.

Do not use the OUTEN ALL bit when using the OUTEN bit in the DAC Control Registers.

DC_DCALL

When set, Powers up the DC-DC on all 4 channels Simultaneously.

To Power down the DC-DCs all channels outputs must first be disabled.

Do not use the DC_DCALL bit when using the DC_DC bit in the DAC Control Registers.