ISL6595 datasheet(11/22 Pages) INTERSIL

11 / 22 page

FN9192.2

December 4, 2008

algorithm compensates for variations in low-side FET

rDS(ON), parasitic inductance and resistance by regulating to

a low voltage level, putting a known current load through

each phase individually and compensating for the current

sense gain and offset error, as well as changes in

temperature. Alternatively, default compensation values can

be used, or the compensation values can be computed

during system test and stored in memory. The external

current load needed to perform calibration can be

implemented with a precision resistor and N-Channel FET.

The voltage across the resistor is sensed and the N-Channel

FET gate voltage is adjusted through an internal op amp

loop to provide the desired precision current. The calibration

current level and the voltage level at which the calibration is

performed are both programmable.

After the soft-start ramp is completed, the regulator enters

the active regulation state and the VR_READY pin

transitions from “0” to “1”, indicating that the microprocessor

voltage is within ±10% of the target value.

Shutdown

The ISL6595 also performs a controlled shutdown response

to minimize any voltage undershoot. The shutdown state can

be entered from the soft-start or active regulation states

either through user intervention (de-asserting VR_EN or all

one’s VID), or through a detected fault such as

over-temperature or output overvoltage. During shutdown,

the PWM width is reduced at a steady programmable rate,

and then the power stage is three-stated once the pulse

width reaches 0.

After shutdown is complete, the controller re-enters the

inactive state after a fixed delay. This delay minimizes the

duty cycle associated with autonomous restarts if the fault

that caused the shutdown disappears once the output is

disabled. Alternatively, the fault can be configured so that it

is latched and clearing requires user intervention such as

toggling VR_EN, toggling RESET_N, or cycling power. If this

method is used, the user should ensure adequate delay is

provided to complete the shutdown prior to the start of a new

start-up. The delay may be as short as 2ms, although longer

delays are recommended to minimize the duty cycle in case

there is a fault which causes the start-up and shutdown cycle

to be repeated indefinitely.

Switching Frequency

Timing is provided by an on-chip, factory trimmed,

temperature compensated oscillator.

The ISL6595 operates with a fixed switching frequency (i.e.

the switching frequency is fixed independent of load) that is

configurable between 100kHz and 2MHz. A programmable

divider is used to generate the switching frequency, where

the frequency is given by Equation 1:

where fSW is the switching frequency, 156.25MHz is the

nominal frequency of the timing reference oscillator, div_sel

is the programmable divider ratio between 6 and 127, and

Nph is the number of phases between 1 and 6.

Switching frequencies of less than 300kHz and greater than

1.5MHz are supported only for some number of phases

used.

Output Voltage Sensing and Voltage ADC

The ISL6595 is built around a high performance digital

feedback control loop that senses the differential voltage at

the load. This is used to generate the appropriate pulse

width modulated (PWM) waveforms to drive the power

stages and regulate the load voltage.

The differential sense voltage is digitized with a high speed,

high precision analog-to-digital converter (ADC). The

on-chip factory trimmed temperature compensated bandgap

voltage reference ensures the ADC accuracy is well within

the regulator setpoint accuracy requirements. The ADC is

sampled synchronously so that there are 2 ADC samples

per phase per switching cycle, at a frequency given by

Equation 2:

The ADC also includes a post-filter which provides a null at

fSW * (Nph/2), which is the ripple frequency. This ripple null

filter works in conjunction with an internal analog anti-alias

filter. The anti-alias filter is a single pole, 2MHz low pass

filter. The corner frequency can be lowered by adding series

resistors in the board.

Current Sensing and Current ADC

The ISL6595 provides for precise current monitoring in each

power stage, allowing for industry-leading loadline accuracy

for active voltage positioning (AVP). The current in each

power stage is sensed through one of three methods

FIGURE 3. SOFT-START/CALIBRATION SEQUENCE (3-PHASE)

4.0ms/DIV

VCC (500mV/DIV)

CAL_CUR_EN

(2V/DIV)

CAL_CUR_SEN

(100mV/DIV)

VR_READY

(2V/DIV)

156.25MHz

div_sel x Nph

-----------------------------------------------

(EQ. 1)

156.25MHz

div_sel

--------------------------------

(EQ. 2)

ISL6595

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