ISL6595 datasheet(19/22 Pages) INTERSIL

19 / 22 page

FN9192.2

December 4, 2008

For latched shutdown, user intervention to clear the latched

fault is required before a new soft-start can be attempted.

User intervention must come in the form of VR_EN toggle,

RESET_N toggle, or controller power cycle.

In addition to fault reporting, there are additional fault

handling capabilities specific to each fault type that attempts

to provide more graceful fault handling than a shutdown, but

more active than simply reporting. The specific fault

detection capability and alternate fault handling capability is

as follows:

IUVP: The V12_SEN input continuously senses the +12V

supply through a nominally TBD:1 resistive divider. A

comparator with a programmable threshold is used to

indicate an undervoltage condition. IUVP can be used to

independently provide either an undervoltage lockout prior to

soft-start, or to both provide a lockout and force a shutdown

during active regulation.

OOVP/OUVP: Programmable comparators continuously

monitor the VSEN inputs to detect an output overvoltage or

undervoltage condition. The OOVP voltage threshold is set

relative to VID while OUVP uses a fixed threshold. OOVP is

enabled during soft-start and active regulation, while OUVP

is enabled only during active regulation.

OCP: The OCP (overcurrent protection) continuously

monitors all channel currents to determine whether any of

the currents are greater than a programmable threshold.

Two mechanisms work independently to control overcurrent

conditions. A cycle-by-cycle current limit operates by

disabling a channel for one cycle when its current exceeds

the threshold. A second mechanism monitors the average

current for an overcurrent condition. A programmable

threshold sets a current limit at which a steeper loadline is

implemented, quickly reducing the output voltage downward

as the current increases. Both of these mechanisms allow

hiccup mode overcurrent protection, where the controller

continues to try to provide a regulated output voltage while in

overcurrent. Alternatively, a threshold can be set where the

overcurrent condition will cause the controller to initiate

shutdown.

Over-Temperature Alert/Shutdown: Both the internal and

external temperature monitors are able to provide fault

telemetry in order to shut down the VR in an

over-temperature condition. Two programmable thresholds

are available for temperature faults. Crossing of the first

threshold can be used to only generate a fault report.

Crossing the second threshold can be used to cause a

shutdown to occur.

CRC Failure: The integrity of loading the configuration from

the NVM to the controller’s registers is checked through a

cyclic redundancy code (CRC) check of the data contents. A

CRC failure prevents the controller from leaving the inactive

state.

Calibration Failure: Calibration failure is detected as the

inability to achieve a regulation target in the given

time-frame. These failures typically indicate a component is

damaged or missing.

I2C Interface

All operating parameters in the ISL6595 are configurable via

the I2C interface. Status can also be read back via the same

interface. The ISL6595 operates as a slave at a standard

speed of 100kHz.

Three transactions are supported on the I2C interface:

1. Set current address,

2. Write register,

3. Read register from current address.

All transactions start with a control byte sent from the I2C

master device. The control byte begins with a Start condition,

followed by 7-bits of slave address. The last bit sent by the

master is the R/W bit and is 0 for a write. If any slaves on the

I2C bus recognize their address, they will Acknowledge by

pulling the serial data line low for the last clock cycle in the

control byte. If no slaves exist at that address or are not

ready to communicate, the data line will be 1, indicating a

Not Acknowledge condition. The ISL6595 address on the

I2C bus is 1110_000 or 1110_001, with the LSB set by the

input pin SADDR.

To write a register in the ISL6595, the master sends a control

byte with the R/W bit set to 0, indicating a write. If it receives

an Acknowledge from the ISL6595 it sends a byte

representing the address MSB. The ISL6595 will respond

with an Acknowledge. The master then sends a byte

representing the address LSB. The ISL6595 will respond

with an Acknowledge. The master then sends a byte

representing the data MS-byte to be written at the current

address. The ISL6595 will respond with an Acknowledge.

The master then sends a byte representing the data LS-byte

to be written at the current address. The ISL6595 will

respond with an Acknowledge. The master then issues a

Stop condition, indicating to the ISL6595 that the current

transaction is complete.

To set the current 16-bit address in the ISL6595, the master

sends a control byte with the R/W bit set to 0, indicating a

write. If it receives an Acknowledge from the ISL6595 it

sends a byte representing the address MS-byte. The

ISL6595 will respond with an Acknowledge. The master then

sends a byte representing the address LS-byte. The

ISL6595 will respond with an Acknowledge. The master then

issues a Stop condition, indicating to the ISL6595 that the

current transaction is complete. Any read commands issued

to the ISL6595 will return data from this address.

To read a register from the ISL6595, the master first sets the

address to read from. It then sends a control byte with the

R/W-bit set to 1, indicating a read. If it receives an

Acknowledge from the ISL6595 it send 8-clocks but does not

ISL6595

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