ISL6595 datasheet(13/22 Pages) INTERSIL

13 / 22 page

FN9192.2

December 4, 2008

External Temperature Sense

When configured to sense temperature from an external

thermistor, the temperature sense input, TEMP_SEN, is set

at virtual ground with a fixed offset of 300mV. An external

negative TC thermistor is tied to ground, generating the input

current for the measurement. A series and shunt resistor

network should be used to scale the resultant current to the

proper range. The current range is the same as the current

sense inputs, from 0µA to 275µA in 4.3µA steps.

The ADC measurements are converted to temperature using

a programmable 4-segment piece-wise linear table while the

internal proportional-to-absolute temperature (PTAT)

reference is digitized directly, using a linear curve fit. Both

internal and external temperature measurements are

multiplexed through the current ADC at a low frequency,

providing run-time internal and external temperature

information to perform temperature compensation, reporting,

alerts and shutdown.

Digital Control Loop and PWM Generation

The digital control loop uses a proportional, integral, and

derivative (PID) compensator to drive the digitized sense

voltage to the desired target. An additional second

derivative gain term and a 2nd order post-filter provide

additional high order zeros and poles to further refine the

wideband characteristics of the loop. All loop parameters are

programmable over a wide range of values, allowing loop

bandwidths of 10kHz to 300kHz to be attained depending on

the number and type of power stages used.

The effective transfer function of the compensator is given

by Equation 7:

where:

Ki, Kp, Kd, and Kd2 are the integral, proportional,

derivative, and second derivative gain terms

Kfd1 and Kfd2 are the coefficients of a second order all

pole low pass post-filter

Kmod is a programmable maximum duty cycle scaling

term

Nph is the number of phases and div_sel is the divider

ratio setting the switching frequency

VIN is the power stage input voltage, typically 12V

Q is the ADC step size, 3.125mV

The control loop operates at the same frequency as the

voltage ADC, which is synchronous to the switching

frequency and given by Equation 8:

The compensator digital output is converted to a pulse width

using a digital counter based pulse width modulator. The

pulse width modulator uses two successive samples to

modulate the leading edge and then the trailing edge of a

pulse. The modulator provides for monotonic edge

placements with a resolution of 100ps. The next two

samples are then used to modulate the next phase in the

firing sequence. The pulse width modulator is capable of

setting a maximum duty cycle limit, overlapping adjacent

phases, a minimum pulse width of 13ns, and also producing

zero pulse width with minimal glitching.

Voltage Identification Codes

The target voltage is provided by external parallel 8-bit

voltage identification (VID) inputs. The ISL6595 is fully

compliant with VRD/VRM 11.0 deglitching and dynamic VID

stepping requirements.

ISL6594

ISL6595

VIN

ISEN+

ISEN-

VOUT

PWM

ADC

FIGURE 4. DIFFERENTIAL DCR SENSE

()

–

------------------

–

() K

d2 1z

–

()

⎝⎠

⎜⎟

⎛⎞

(EQ. 7)

fd1

fd2

()

fd1z

–

fd1z

–

----------------------------------------------------------

⎝⎠

⎜⎟

⎛⎞

mod

ph div_sel

⋅

-----------------------------------

⎝⎠

⎜⎟

⎛⎞ V

---------

⎝⎠

⎛⎞

2∗Nph*fsw

156.25MHz/div_sel

(EQ. 8)

ISL6595

ISL6595 Datasheet(PDF) 13 Page - Intersil Corporation

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