ISL6595 datasheet(12/22 Pages) INTERSIL

12 / 22 page

FN9192.2

December 4, 2008

supported by the ISL6595. These are single-ended rDS(ON)

sense of the low-side FET, differential rDS(ON) sense of the

low-side FET, or differential DCR sense of the buck inductor.

The sensed current is digitized using a multiplexed current

ADC.

For low-side rDS(ON) current sense applications, the ISENx+

pin is held at virtual ground with a programmable offset from

25mV to 100mV. An external sense resistor is connected to

the drain of the low side FET to monitor the current in this

device. The current sourced from the input is then given in

Equation 3:

where input current is digitized with the ADC with an

effective ADC range of 0µA to 275µA in 4.3µA steps.

For DCR current sense applications, a resistor in series with

a capacitor is placed across the inductor for each phase. In

this configuration, the resistor is tied to the FET side of the

inductor while the capacitor is tied to the load side of the

inductor. If the RC values are chosen such that the RC time

constant matches the L/DCR time constant, the resultant

voltage appearing across the capacitor will equal the voltage

across the inductor series resistance and thus represent the

current flowing through the inductor. In this application, a

sense resistor is then placed from the ISENx+ pin to the load

side of the capacitor while the ISENx- pin in placed on the

FET side of the capacitor. The current sourced from the input

is then given in Equation 4:

where Input current is digitized with the ADC with an

effective ADC range of 0µA to 275µA in 4.3µA steps.

Differential rDS(ON) Current Sense

The positive current sense inputs (ISEN1+ to ISEN6+) are

held at a virtual ground with a programmable offset from

25mV to 100mV, in 25mV steps. The negative current sense

inputs (ISEN1- to ISEN6-) should be tied to the ground plane

local to the low side FET being sensed to eliminate the

effects of ground differences between the FET and the

ISL6595. The large voltage swing at the drain of the low side

FET is eliminated by using a series resistor, converting the

signal to a current equal to that in Equation 5:

where ISENSE is the current sourced by the sense input,

Voffset is the programmable offset, VDS is the voltage

across the low side FET, and RSENSE is an external resistor

whose value is chosen to scale the input depending on the

expected rDS(ON).

The input current is mirrored and multiplexed, then digitized

by the 6-bit current ADC with an effective input range of

0µA to 275µA in 4.3µA steps. The ADC samples the current

in each phase once per switching cycle, and the sampling

instant can be varied using a programmable delay, such that

sampling in the middle of the ON-cycle can be guaranteed.

The current in the power stage can then be inferred from the

current ADC measurement if the drain-source resistance

(rDS(ON)) of the FET is known. The rDS(ON) of each FET

can be either programmed as a default value, or it can be

determined by running the calibration routine either one time

at system test or every time the system starts up. Calibration

is performed by providing a known current load while the

regulator is on and correcting the gain and offset of the

current measurement. This requires the use of a precision

external current source consisting of a dedicated calibration

FET and sense resistor. The ISL6595 senses the voltage

across the resistor and provides a variable voltage to drive

the gate of the calibration FET, varying its rDS(ON) such that

the current through the FET and resistor are under closed

loop control. The calibration current and voltage level at

which calibration occurs are programmable, and the

calibration routine can be bypassed if the default values are

to be used. The rDS(ON) value is compensated for

temperature drift using either the on-chip temperature sense

or an external thermistor that can be placed close to the

power stage.

Differential DCR Current Sense

For DCR current sense applications, a resistor in series with

a capacitor is placed across the inductor for each phase. In

this configuration, the resistor is tied to the FET side of the

inductor while the capacitor is tied to the load side of the

inductor. If the RC values are chosen such that the RC time

constant matches the L/DCR time constant, the resultant

voltage appearing across the capacitor will equal the voltage

across the inductor series resistance and thus represent the

current flowing through the inductor. In this application, a

sense resistor is then placed from the ISENX+ pin to the

load side of the capacitor while the ISENX- pin in placed on

the FET side of the capacitor. The current sourced from the

input is then given in Equation 6:

where input current is digitized with the ADC with an

effective ADC range of 0µA to 275µA in 4.3µA steps.

ISEN

OFFSET

DS ON

()

–

()

SEN1

-----------------------------------------------------------------

(EQ. 3)

ISEN

OFFSET

DCR

–

()

SEN

------------------------------------------------------

(EQ. 4)

ISENSE

OFFSET

–

()

SENSE

-------------------------------------------------

(EQ. 5)

ISEN

OFFSET

DCR

–

()

SENSE

------------------------------------------------------

(EQ. 6)

ISL6595

ISL6595 Datasheet(PDF) 12 Page - Intersil Corporation

ISL6595 Datasheet(HTML) 12 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL