E6000 datasheet(28/118 Pages) INTEL

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Electrical Specifications

Datasheet

2.7.3.1

GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the

processor silicon. See Table 9 for details on which GTL+ signals do not include on-die

termination.

Valid high and low levels are determined by the input buffers by comparing with a

reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+

reference voltage (GTLREF) should be generated on the system board using high

precision voltage divider circuits.

Table 13.

CMOS Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes1

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

VIL

Input Low Voltage

-0.10

VTT * 0.30

2, 3

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low

value.

3. The VTT referred to in these specifications refers to instantaneous VTT.

VIH

Input High Voltage

VTT * 0.70

VTT + 0.10

3, 4, 5

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high

value.

5. VIH and VOH may experience excursions above VTT.

VOL

Output Low Voltage

-0.10

VTT * 0.10

VOH

Output High Voltage

0.90 * VTT

VTT + 0.10

3, 6, 5

6. All outputs are open drain.

IOL

Output Low Current

1.70

4.70

3, 7

7. IOL is measured at 0.10 * VTT. IOH is measured at 0.90 * VTT.

IOH

Output High Current

1.70

4.70

3, 7

ILI

Input Leakage Current

N/A

± 100

µA

8. Leakage to VSS with land held at VTT.

ILO

Output Leakage Current

N/A

± 100

µA

9. Leakage to VTT with land held at 300 mV.

Table 14.

GTL+ Bus Voltage Definitions

Symbol

Parameter

Min

Typ

Max

Units Notes1

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

GTLREF_PU

GTLREF pull up resistor

124 * 0.99

124

124 * 1.01

2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each

GTLEREF land).

GTLREF_PD

GTLREF pull down resistor

210 * 0.99

210

210 * 1.01

RTT

Termination Resistance

3. RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.

COMP[3:0]

COMP Resistance

49.40

49.90

50.40

4. COMP resistance must be provided on the system board with 1% resistors. See the applicable

platform design guide for implementation details. COMP[3:0] and COMP8 resistors are tied to

VSS.

COMP8

COMP Resistance

24.65

24.90

25.15

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