81341 datasheet(13/89 Pages) INTEL

13 / 89 page

December 2007

Datasheet

Order Number: 315038-003US

Features—Intel® 81341 and 81342

2.1.6

DDR2 Memory Controller

The DDR2 Memory Controller allows direct control of the 400/533 MHz DDR2 SDRAM

memory subsystem. It features programmable chip selects and support for error-

correction codes (ECC). The DDR2 Memory Controller is multi-ported with the following

interfaces: south internal bus, ADMA controllers, north internal bus. The memory

controller interface configuration support includes unbuffered DIMMs, registered

DIMMs, and discrete DDR2 SDRAM devices.

2.1.7

SRAM Memory Controller

The SRAM Memory Controller allows direct control of a 1.0 MByte SRAM memory

subsystem. It supports error correction codes (ECC). The SRAM is used to store

firmware code, I/O exchange contexts and for general-purpose data storage.

2.1.8

Peripheral Bus Interface

The Peripheral Bus Interface Unit is a data communication path to the flash memory

components or other peripherals of a 81341 and 81342 I/O Processors hardware

system. The PBI includes support for either 8- or 16-bit devices. To perform these tasks

at high bandwidth, the bus features a burst-transfer capability which allows successive

8/16-bit data transfers.

2.1.9

I2C Bus Interface Units

There are three I2C (Inter-Integrated Circuit) Bus Interface Units that allow the Intel

XScale® processor to serve as a master and slave device residing on the I2C bus. The

I2C0 allows the I/O processor to interface to a Storage Enclosure Processor (SEP). The

bus allows the 81341 and 81342 I/O Processors to interface to other I2C peripherals

and microcontrollers for system management functions. For more information, refer to

I2C Peripherals for Microcontrollers (Philips Semiconductor)1.

2.1.10

UART Units

The 81341 and 81342 I/O Processors includes two UART units. The UART units allow

the two Intel XScale® processors to serve as a master and slave device residing on the

UART bus. The UART units use a serial bus consisting of a two-pin interface. UART0

allows the 81341 and 81342 I/O Processors to interface to a console port for

debugging. Also refer to the National Semiconductor* 16550 device specification2.

2.1.11

Interrupt Controller Unit

Each Intel XScale® processor supports an Interrupt Controller Unit (ICU). The ICU

aggregates interrupt sources both external and internal sources of the 81341 and

81342 I/O Processors to the Intel XScale® processor. The ICU supports high-

performance interrupt processing with direct interrupt service routine vector generation

on a per-source basis. Each source has programmability for masking, processor

interrupt input, and priority.

2.1.12

XSI System Controller

Each XSI bus (north and south) employs an XSI system controller. The XSI system

controller observes all the address or data bus requests from requestors and

completors connected to the XSI bus. The XSI system controller handles XSI address

1. http://www.semiconductors.philips.com/buses/i2c/

2. http://www.national.com/pf/PC/PC16550D.html

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