81341 datasheet(21/89 Pages) INTEL

21 / 89 page

December 2007

Datasheet

Order Number: 315038-003US

Package Information—Intel® 81341 and 81342

P_IRDY#

I/O

Sync (P)

Rst (P)

ActLow

PCI Bus Initiator Ready indicates the initiating agent’s ability to

complete the current data phase of the transaction. During a write,

it indicates that valid data is present on the address/data bus.

During a read, it indicates that the processor is ready to accept the

data.

P_TRDY#

I/O

Sync (P)

Rst (P)

ActLow

PCI Bus Target Ready indicates the target agent’s ability to

complete the current data phase of the transaction. During a read,

it indicates that valid data is present on the address/data bus.

During a write, it indicates that the target is ready to accept the

data.

P_STOP#

I/O

Sync (P)

Rst (P)

ActLow

PCI Bus Stop indicates a request to stop the current transaction on

the PCI bus.

P_DEVSEL#

I/O

Sync (P)

Rst (P)

ActLow

PCI Bus Device Select is driven by a target agent that has

successfully decoded the address. As an input, it indicates whether

or not an agent has been selected.

P_SERR#

I/O

Sync (P)

Rst (P)

ActLow

PCI Bus System Error is driven for address parity errors on the PCI

bus.

P_RSTOUT#

Async

ActLow

PCI Reset Out is based on

P_RST# and WARM_RST#. It brings

PCI-specific registers, sequencers, and signals to a consistent state.

When either

P_RST# or WARM_RST# is asserted, it causes

P_RSTOUT# to assert and:

• PCI output signals are driven to a known consistent state.

• PCI bus interface output signals are three-stated.

• Open-drain signals such as P_SERR_# are floated.

P_RSTOUT# can be asynchronous to P_CLK when asserted or

deasserted.

P_PERR#

I/O

Sync (P)

Rst (P)

ActLow

PCI Bus Parity Error is asserted when a data parity error occurs

during a PCI bus transaction.

P_M66EN

PCI Bus 66 MHz Enable indicates the speed of the PCI bus. When

this signal is sampled high, the PCI bus speed is 66 MHz; when low,

the bus speed is 33 MHz.

P_IDSEL

Sync (P)

PCI Bus Initialization Device Select is used to select the Intel®

81341 and Intel® 81342 I/O Processors during a configuration read

or write.

Note: In central resource mode this pin must be pulled down to

with an external 4.7K ohm 5%, 1/16 W resistor for

proper operation.

P_GNT[0]# /

P_REQ#

Sync (P)

ActLow

PCI Bus Grant:

• Internal arbiter mode: This is one of four output grant signals

from the internal arbiter.

PCI Bus Request:

• External arbiter mode: This is the output request signal for the

ATU.

P_REQ[0]# /

P_GNT#

Sync (P)

Rst (P)

ActLow

PCI Bus Request:

• Internal arbiter mode: This is one of four input request signals

to the internal arbiter.

PCI Bus Grant:

• External arbiter mode: This is the input grant signal to the ATU.

Table 5.

PCI Bus Signals (Sheet 2 of 3)

Name

Count

Type

Description

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